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參數(shù)資料
| 型號(hào)： | 82C836A-20 |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 151/205頁(yè) |
| 文件大?。?/td> | 3878K |
| 代理商： | 82C836A-20 |
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mid-T1. Since the earliest that the 82C836 could assert -READY again is during the
third T2 after T1 (early wait state enabled), the first T2 after T1 is available for external
logic to assert -READY without conflicting with the 82C836.
The 82C836 samples -LBA and -READY at the end of the first T2 after T1. -READY
active at that time terminates the cycle. -LBA active at that time causes the 82C836 to
look for -READY at the end of each subsequent T2 state. The cycle terminates when the
external logic asserts -READY. -LBA is ignored and is ‘‘don’t care’’ at all times other
than at the end of the first T2 after T1.
If the external logic asserts both -LBA and -READY at the end of the first T2 (not a valid
combination), the cycle terminates just as if -READY alone had been asserted.
The net performance effect of local cache is as follows:
Greatly increased percentage of two T-state memory reads due to high cache hit ratio
(without cache, two T-state memory reads would still be possible in pipelined page
mode, but the hit ratio would be considerably lower than with a cache).
Cache read misses increase from two T-state minimum to four T-states for -CAS only
memory reads. Since cache read misses occur far less often with cache than without
it, this penalty for cache read misses should have only a minor impact on overall
system performance.
Page hit writes can occur in zero wait states, as compared to one wait state minimum
in noncache modes.
Coprocessor Timing
Figure 11-11 shows the relationship between the coprocessor busy and error signals
and the busy signal sent to the CPU. Normally, -BUSY to the CPU simply follows
-NPBUSY from the coprocessor. When a coprocessor exception occurs (-NPERR
asserted), -BUSY to the CPU is latched (active) until the CPU acknowledges it by
performing an I/O write to prot F0H. This protocol is AT-compatible and differs from
the ‘‘generic’’ coprocessor interface internal to the 80386sx CPU. In particular, the
-ERROR input to the CPU should be tied high, and AT-compatible software will rely
on interrupt level 13 for reporting coprocessor exceptions. The -NPERR signal from
the coprocessor is eventually cleared by I/O writes to the coprocessor sometime after
the output to port F0H.
Figure 11-11.
Coprocessor Timing
System Timing Relationships
CPU Access to AT-Bus
I
Chips and Technologies, Inc.
P R E L I M I N A R Y
Revision 3.0
11-19
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836B | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
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