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參數(shù)資料
| 型號(hào)： | 82C836A-20 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip 386sx AT |
| 中文描述： | 單芯片386sx在 |
| 文件頁(yè)數(shù)： | 114/205頁(yè) |
| 文件大小： | 3878K |
| 代理商： | 82C836A-20 |
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Table 10-2.
Index 40H----82C836 Version, Read Only
Bit
Name
Description
7-4
Family Type
Identifies specific part in pin-compatible family. SCATsx denoted by 0001.
3-0
Device Revision
Code
Identifies revision level of the 82C836 silicon, starting with 0000. The
82C836B has revision code 0100; the 82C836A has code 0011.
Table 10-3.
Index 41H----Channel Environment
Bit
Name
Description
7
Fast Refresh
This bit controls an improvement in HOLD timing to reduce total HLDA
time during refresh. Up to 1% performance improvement possible.
0 = Enable fast refresh (default)
1 = Disable; follow revision 1 refresh timing
This bit is intended to remain zero except for test purposes.
6
Early READY
Enable
Allows external devices to assert READY during the first T2 after T1 to
terminate the memory cycle after only two T-states. Enables ‘‘Early Wait
State’’ for local memory read not ‘‘claimed’’ by early READY.
1 = Enable*
0 = Disable (default)
5
LBA Enable
Allows external devices to assert LBA (0WS pin) during the first T2 after T1
to prevent the 82C836 from starting a memory cycle. Enables Early Wait
State for local memory read not claimed by LBA.
1 = Enable*
0 = Disable (default)
If both Early READY and LBA are enabled, there will still be only one early
wait state for unclaimed local memory reads.
4
Bus Convert
Enable
Enable conversion of 8-bit AT bus reads into 16-bit reads so that a local
cache, if present, can cache 16 bits at a time.
1 = Enable
0 = Disable (default)
This feature does not apply to 8-bit AT bus memory resources residing in
the first 1MB. Also, the usual AT-compatible conversion of ‘‘even word’’
accesses into paired byte operations is not affected by this bit. This bit has
no effect unless bit 6 is set.
3-2
BUSCLK SEL
Selects AT bus clock.
00 = Selects BUSCLK as CXIN/4
01 = Selects BUSCLK as CXIN/5 (default)
10 = Selects BUSCLK as CXIN/6
11 = (Reserved)
1-0
Refresh
Width
These bits specify -XMEMR pulse width during a refresh cycle. These pulse
widths are derived from OSC. The width of -XMEMR directly affects the
overall bus cycle time for refresh operations.
00 = 104ns
01 = 210ns
10 = 280ns (default)
11 = 350ns
*
Bits 5 and 6 must remain zero if CPU pipeline mode is enabled.
I
Configuration Registers
82C386 CHIPSet Data Sheet
10-2
Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82C836B | Single-Chip 386sx AT |
| 82C862 | FireLink USB Dual Controller Quad Port USB |
| 82C931 | Plug and Play Integrated Audio Controller |
| 82S09 | 576-BIT BIPOLAR RAM (64 X 9) |
| 82S19 | 576-BIT BIPOLAR RAM (64 X 9) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82C836B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip 386sx AT |
| 82C83H | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver |
| 82C84 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Clock Generator Driver |
| 82C84A/B | 制造商: 功能描述: 制造商:undefined 功能描述: |
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