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參數(shù)資料
| 型號： | 7C185-12 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 8K x 8 Static RAM |
| 中文描述： | 8K的× 8靜態(tài)RAM |
| 文件頁數(shù)： | 5/11頁 |
| 文件大?。?/td> | 197K |
| 代理商： | 7C185-12 |
CY7C185
Document #: 38-05043 Rev. *A
Page 5 of 11
Switching Waveforms
10. Device is continuously selected. OE, CE
1
= V
IL
. CE
2
= V
IH
.
11.
WE is HIGH for read cycle.
12. Data I/O is High Z if OE = V
, CE
= V
, WE = V
,
or CE
=V
.
13. The internal write time of the memory is defined by the overlap of CE
LOW, CE
HIGH and WE LOW. CE
and WE must be LOW and CE
must be HIGH
to initiate write. A write can be terminated by CE
1
or WE going HIGH or CE
2
going LOW. The data input set-up and hold timing should be referenced to the
rising edge of the signal that terminates the write.
14. During this period, the I/Os are in the output state and input signals should not be applied.
ADDRESS
DATA OUT
PREVIOUS DATA VALID
DATA VALID
t
RC
t
AA
t
OHA
Read Cycle No.1
[10,11]
50%
50%
DATA VALID
t
RC
t
ACE
t
DOE
t
LZOE
t
LZCE
t
PU
HIGH IMPEDANCE
IMPEDANCE
ICC
ISB
t
HZOE
t
HZCE
t
PD
OE
HIGH
DATA OUT
V
CC
SUPPLY
CURRENT
CE
1
CE
2
Read Cycle No.2
[12,13]
t
HD
t
SD
t
PWE
t
SA
t
HA
t
AW
t
WC
t
HZOE
DATA
IN
VALID
CE
2
CE
1
OE
WE
DATA I/O
t
SCEI
t
SCE2
ADDRESS
NOTE 14
[11,13]
Write Cycle No. 1 (WE Controlled)
相關PDF資料 |
PDF描述 |
|---|---|
| 7C185-15 | IC 16-BIT BUFF/LINE DRV 48 TSSOP |
| 7C185-20 | 8K x 8 Static RAM |
| 7C185-25 | 16-Bit Buffer/Line Driver |
| 7C185-35 | IC 16-BIT BUFF/LINE DVR 48-SSOP |
| 7C187-15 | 64K x 1 Static RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 7C185-15 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Static RAM |
| 7C185-20 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Static RAM |
| 7C185-25 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Static RAM |
| 7C185-35 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:8K x 8 Static RAM |
| 7C185-35VCT | 制造商:undefined 功能描述: |
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