參數(shù)資料
型號(hào)： 7C146-55
廠商： Cypress Semiconductor Corp.
英文描述： 2Kx8 Dual-Port Static RAM
中文描述： 2Kx8雙端口靜態(tài)存儲(chǔ)器
文件頁(yè)數(shù)： 8/18頁(yè)
文件大?。?/td> 339K
代理商： 7C146-55
CY7C132/CY7C136
CY7C142/CY7C146
8
Write Cycle No.1 (OE Three-States Data I/Os-Either Port)
[15, 23]
Write Cycle No. 2 (R/W Three–States Data I/Os-Either Port)
[15, 24]
Notes:
23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance and for data
to be placed on the bus for the required t
.
24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high-impedance state.
Switching Waveforms
(continued)
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
CE
R/W
ADDRESS
OE
D
OUT
DATA
IN
C132-10
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D
OUT
DATA
IN
t
LZWE
DATA VALID
C132-11
相關(guān)PDF資料
PDF描述
7C136-15 Hook-Up Wire; Conductor Size AWG:20; No. Strands x Strand Size:7 x 28; Jacket Color:Black; Approval Bodies:UL, CSA; Approval Categories:UL AWM Styles 1007, 1565; CSA Types TR-64, TRSR-64; JQA-F; Passes VW-1 Flame Test RoHS Compliant: Yes
7C1351-40 128Kx36 Flow-Through SRAM with NoBL TM Architecture
7C1351-50 128Kx36 Flow-Through SRAM with NoBL TM Architecture
7C1351-66 128Kx36 Flow-Through SRAM with NoBL TM Architecture
7C1359A-100 256K x 18 Synchronous-Pipelined Cache Tag RAM
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