參數(shù)資料
型號(hào)： 7B991RPFS
廠商： MAXWELL TECHNOLOGIES
元件分類： 時(shí)鐘及定時(shí)
英文描述： Programmable Skew Clock Buffer (PSCB)
中文描述： PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), DFP32
封裝： RAD PAK, DFP-16
文件頁(yè)數(shù)： 13/17頁(yè)
文件大?。?/td> 253K
代理商： 7B991RPFS
M
13
All data sheets are subject to change without notice
2002 Maxwell Technologies.
All rights reserved.
Programmable Skew Clock Buffer (PSCB)
7B991
09.23.02 Rev 4
results in a 40 MHz waveformat these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of
phase on their rising edge. This will allow the designer to use the rising edges of the
frequency and
frequency
outputs without concern for rising-edge skew The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by
programmng their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the fre-
quency of the fastest output.
F
IGURE
9. F
REQUENCY
D
IVIDER
C
ONNECTIONS
Figure demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for
zero skew 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of
the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the
frequency and
frequency without
concern for skew msmatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In
this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency
output is running at 20 MHz.
F
IGURE
10. M
ULTI
-F
UNCTION
C
LOCK
D
RIVER
Figure shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs
and outputs that offer divide-by-2 and divide-by-4 timng. An inverted output allows the systemdesigner to clock differ-
ent sub-systems on opposite edges, without suffering fromthe pulse asymmetry typical of non-ideal loading. This
function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the
skew specification.
The divided outputs offer a zero-delay divider for portions of the systemthat need the clock to be divided by either two
or four, and still remain within a narrow skew of the
“
1X
”
clock. Without this feature, an external divider would need to
be added, and the propagation delay of the divider would add to the skew between the different clock signals.
相關(guān)PDF資料
PDF描述
7B991 Programmable Skew Clock Buffer (PSCB)
7BT2F9A-361 HIGH CAPACITY ENVIRONMENTALLY SEALED
7BT2 HIGH CAPACITY ENVIRONMENTALLY SEALED
7BT2F15A-361 HIGH CAPACITY ENVIRONMENTALLY SEALED
7BT2F15A-362 HIGH CAPACITY ENVIRONMENTALLY SEALED
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