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參數(shù)資料
| 型號： | 79RC5000 |
| 廠商： | Integrated Device Technology, Inc. |
| 元件分類： | 64位微處理器 |
| 英文描述： | MULTI-ISSUE 64-BIT MICROPROCESSOR |
| 中文描述： | 多發(fā)行64位微處理器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 297K |
| 代理商： | 79RC5000 |
2 of 15
April 10, 2001
79RC5000
The RC5000 serves many performance critical embedded applica-
tions, such as high-end internetworking systems, color printers, and
graphics termnals.
The RC5000 is optimzed for high-performance applications, with
special emphasis on systembandwidth and floating point operations,
through integration of high-performance computational units and a high-
performance memory hierarchy. For this class of application, the result
is a relatively low-cost CPU capable of approximately 330 Dhrystone
MIPS.
IDT’s objectives in offering the RC5000 include:
N
Offering a high performance upgrade path to existing embedded
customers in the internetworking, office automation and
visualization markets.
N
Providing a significant improvement in the floating- point
performance currently available in a moderately priced MIPS
CPU.
N
Providing improvements in the memory hierarchy of desktop
systems by using large primary caches and integrating a
secondary cache controller.
N
Enabling improvements in performance through the use of the
MIPS-IV ISA.
The RC5000 recognizes two general classes of instructions for multi-
issue:
N
Floating-point ALU
N
All others
These instruction classes are pre-decoded by the RC5000, as they
are brought on-chip. The pre-decoded information is stored in the
instruction cache.
Assumng that there are no pending resource conflicts, the RC5000
can issue one instruction per class per pipeline clock cycle. Note that
this broad separation of classes insures that there are no data depen-
dencies to restrict multi-issue.
However, long-latency resources in either the floating-point ALU (e.g.
DIV or SQRT instructions) or instructions in the integer unit (such as
multiply) can restrict the issue of instructions. Note that the R5000 does
not performout-of-order or speculative execution; instead, the pipeline
slips until the required resource becomes available.
There are no alignment restrictions on dual-issue instruction pairs.
The RC5000 fetches two instructions fromthe cache per cycle. Thus, for
optimal performance, compilers should attempt to align branch targets
to allow dual-issue on the first target cycle, since the instruction cache
only performs aligned fetches.
The RC5000 implements the MIPS-IV 64-bit ISA, including CP1 and
CP1X functional units (and their instruction set).
The RC5000 is a limted dual-issue machine that utilizes a traditional
5-stage integer pipeline. This basic integer pipeline of the RC5000 is
illustrated in Figure 1. The integer instruction execution speed is tabu-
lated (in number of pipeline clocks) as follows:
The RC5000’s short pipeline keeps the load and branch latencies
very low The caches contain special logic that allows any combination
of loads and stores to execute in back-to-back cycles without requiring
pipeline slips or stalls. (This assumes that the operation does not mss
in the cache.)
Load
2
1
Store
2
1
MULT/MULTU
8
8
DMULT/DMULTU
12
12
DIV/DIVU
36
36
DDIV/DDIVU
68
68
Other Integer ALU
1
1
Branch
2
2
Jump
2
2
Table 1 Integer Instruction Execution Speed
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相關(guān)代理商/技術(shù)參數(shù) |
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