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April 10, 2001
2001 Integrated Device Technology, Inc.
DSC 5719
MULTI-ISSUE
64-BIT MICROPROCESSOR
N
Dual issue super-scalar execution core
–
250 MHz frequency
–
Dual issue floating-point ALU operations with other instruction
classes
–
Traditional 5-stage pipeline, mnimzes load and branch laten-
cies
N
Single-cycle repeat rate for most floating point ALU
operations
N
High level of performance for a variety of applications
–
High-performance 64-bit integer unit achieves 330 dhrystone
MIPS (dhrystone 2.1)
–
Ultra high-performance floating-point accelerator directly
implementing single- and double-precision operations
achieves 500mflops
–
Extremely large on-chip primary cache
–
On-chip secondary cache controller
N
MIPS-IV 64-bit ISA for improved computation
–
Compound floating-point operations for 3D graphics and
floating-point DSP
–
Conditional move operations
N
Large on-chip TLB
N
Active power management, including use of WAIT operation
N
Large, efficient on-chip caches
–
32KB Instruction Cache, 32KB Data Cache
–
2-set associative in each cach
–
Virtually indexed and physically tagged to mnimze cache
flushes
–
Write-back and write-through selectable on a per page basis
–
Critical word first cache mss processing
–
Supports back-to-back loads and stores in any combination at
full pipeline rate
N
High-performance memory system
–
Large primary caches integrated on-chip
–
Secondary cache control interface on-chip
–
High-frequency 64-bit bus interface runs up to 125MHz
–
Aggregate bandwidth of on-chip caches, systeminterface of
5.6GB/s
–
High-performance write protocols for graphics and data
communications
N
Compatible with a variety of operating systems
–
Windows CE
–
Numerous MIPS-compatible real-time operating systems
N
Uses input system clock, with processor pipeline clock
multiplied by a factor of 2-8
N
Industrial and commercial temperature range
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
Instruction Tag B
ITLB Physical
Write Buffer
Read Buffer
DVA
IVA
F
I
DBus
Tag
AuxTag
IntIBus
FPIBus
ABus
Data Set A
Store Buffer
Phase Lock Loop
Data Tag A
Instruction Set A
DTLB Physical
Instruction Select
Integer Instruction Register
FP Instruction Register
Data Set B
Address Buffer
Instruction Tag A
SysAD
Control
Floating Point Register File
Unpacker/Packer
Joint TLB
Coprocessor 0
SystControl
PC Incrementer
Branch Adder
Instruction TLB Virtual
Program Counter
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
Integer Multiply, Divide
MFDiv, SqRt
Instruction Set B
79RC5000