參數資料
型號： 78Q8430-100IGT/F
廠商： Maxim Integrated Products
文件頁數： 37/88頁
文件大?。?/td> 0K
描述： IC LAN MEDIA ACCESS CTLR 100LQFP
產品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 90
控制器類型： 以太網控制器，MAC/PHY
電源電壓： 3.3V
電流 - 電源： 230mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應商設備封裝： 100-LQFP（14x14）
包裝： 托盤
78Q8430 Data Sheet
DS_8430_001
42
Rev. 1.2
6.7.4.2
Source Address Filtering
Source address filtering can be used to drop frames with a specific address while passing all others.
Table 30 contains the rules on processing source address.
Table 30: Process Source Address Rules
Rule#
PrevHit
PH-Mask
Data
D-Mask
Next
Offset Action
Interrupt Comment
0x2F
0x30
0x70
0x01
DROP
0x00
NOP
0
MC drop
0x2E
0x30
0x70
0x00
MD
0x05
NOP
0
pass other
6.7.4.3
Length/Type Field, MAC Control Frames and IP Header Checksum
Table 31 contains the rules on processing length/type, MAC control frames and start IP header checksum
check.
Table 31: Process Length/Type, MAC Control Frames and Start IP Header Checksum Rules
Rule#
PrevHit
PH-Mask
Data
D-Mask
Next
Offset
Action
Interrupt Comment
0x2D
0x2B
0x7F
0x00
0xFF
MD
0x02
VLAN
0
0x2C
0x00
DONE
0x00
NOP
0
0x2B
0x2E
0x7F
0x81
0xFF
MD
0x00
TDLTH
0
0x2A
0x2B
0x7F
0x00
DONE
0x00
TDLTL
0
0x29
0x2F
0x7C
0x88
0xFF
MD
0x00
TDLTH
0
0x28
0x29
0x7F
0x08
0xFF
MD
0x00
MCTL
0
0x27
0x29
0x7F
0x00
DONE
0x00
TDLTL
0
0x26
0x2F
0x7C
0x00
MD
0x00
TDLTH
0
0x25
0x26
0x7F
0x00
MD
0x00
TDLTL
0
0x24
0x25
0x7F
0x40
0xF0
MD
0x00
IPCK
0
0x23
0x24
0x7E
0x00
MD
0x3F
TXA
0
0x22
0x28
0x7F
0x00
0xFF
MD
0x00
NOP
0
0x21
0x28
0x7F
0x00
DONE
0x00
NOP
0
0x20
0x22
0x7F
0x01
0xFF
MD
0x00
NOP
0
MCTL pause
0x1F
0x22
0x7F
0x00
DONE
0x00
NOP
0
MCTL other
0x1E
0x20
0x7F
0x00
MD
0x00
TDPH
0
0x1D
0x1E
0x7F
0x00
MX
0x00
TDPL
0
0x1C
0x1D
0x7F
0x3D
0xFF
DONE
0x00
PAUSE
0
0x1B
0x1D
0x7F
0x00
DONE
0x00
NOP
0
MCTL pause
with bad SRC
6.7.4.4
Wake on LAN
The packet classification engine can use the WAKE action to signal the host to come out of power down
mode. This is used to implement the Wake-On-LAN feature.
The Power Management Control and Status Register (PMCSR) is used to control the hardware response
to a WAKE action. If the PS field of the PMCSR is zero then all WAKE actions are ignored. The
WAKE action is only honored if the part is currently in a power down mode as determined by the
PS field. If the PME_ENB bit in the PMCSR is set then a valid WAKE action will trigger the assertion of
the PMEB primary output. If the PME_ENB bit is clear then a valid WAKE action will only result in the
normal HIR WAKE interrupt.
When the host is notified of a valid WAKE event, either by the assertion of the PMEB primary output or
assertion of INTB via the WAKE HIR interrupt, the rule that triggered the event can be read from the
Wake Up Status Register (WUSR). A valid WAKE event will also start the Host Not Responding (HNR)
timer. When the host is notified of a WAKE event, it must clear the event by setting the PME bit in the
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