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參數(shù)資料
| 型號(hào)： | 78Q8430-100IGT/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 32/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 控制器類型： | 以太網(wǎng)控制器，MAC/PHY |
| 電源電壓： | 3.3V |
| 電流 - 電源： | 230mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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78Q8430 Data Sheet
DS_8430_001
38
Rev. 1.2
6.7.2
Configuring the CAM
The CAM rules are accessed indirectly one at a time via the CAM Address Register (CAR). The contents
of the rule whose number is indicated by the CAR are available for read and write via the Rule Match
reference word must match in order to trigger the rule, and the RCR contains the control word that is
passed to the control logic when the rule is triggered.
6.7.2.1
Rule Match Register
The RMR contains four fields that control when a rule is triggered: Previous Hit Match and Previous Hit
Mask, Data Match and Data Mask. The mask fields are used to determine which bits in their respective
match field are required to make a match and which bits are ignored. A mask bit value of one means that
the corresponding match bit must be exactly equal to the same bit in the CAM reference word to trigger
the rule. Inversely, a mask bit value of zero means that the corresponding bit in the CAM reference word
is ignored. A special case is that all previous hit mask bits are zero. In this case, the rule is deactivated
and can never be triggered.
6.7.2.2
Rule Control Register
The RCR contains four fields that control the actions taken by the control logic when the rule is triggered:
Byte Offset, Interrupt, Action and Match Control fields.
RCR Byte Offset
The Byte Offset field is generally used to skip over bytes in the frame that are not relevant to the current
classification. When the Byte Offset is non-zero then the classification will skip the number of bytes
indicated. The exception is when the TOC action is used, in which case, the value of the Byte Offset field
is used to initialize the control logic counter and no offset is applied.
An offset value of 0x3F will skip just the right number of bytes to jump over the current IPv4 header.
RCR Interrupt
When the Interrupt bit in the RCR for a given rule is set, then the triggering of the rule will cause an HIR
classification interrupt.
Control Logic Action
The value of the control logic Action field in the RCR determines the action that will be taken by the
control logic when the rule is triggered.
Table 26: Control Logic Actions
Hex
Value
Binary
Value
Name
Action Taken
0x0
00000b
NOP
No action taken.
0x2
00010b
PAUSE
Start the local pause timer.
0x4
00100b
WAKE
Send a wake-up signal to the host and start the HNR timer.
0x6
00110b
IPCK
Start the IP header checksum check and the IP header counter.
0x7
00111b
TIPO
Transfer IP header counter to offset.
0x8
01000b
TDX
‘X’ is assigned the value of the frame data.
0xA
01010b
TAX
‘X’ is assigned the value of the current rule number.
0xC
01100b
TAXH
The high-order nibble of ‘X’ is assigned the value of the low-order nibble
of the current rule number.
0xD
01110b
TAXL
The low-order nibble of ‘X’ is assigned the value of the low-order nibble
of the current rule number.
0x10
10000b
TXA
The classification result is assigned the value of ‘X’.
0x12
10010b
TLXA
The low-order nibble of the classification result is assigned the value of
the low-order nibble of ‘X’.
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