2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號(hào)： 78P2351-DB/CMI
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/42頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 78P2351 COAX CABLE
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
系列： *
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 20 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION (continued)
CONTROL PINS
NAME
PIN
TYPE
DESCRIPTION
FRST
59
CIT
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRST will resume FIFO operation.
Low: FRST assertion.
Float/High: Normal
Because the internal VCO clock and off-chip transmit clocks may not be stable
during transmit power-up, it is recommended to always reset the FIFOs after
powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
RCSL
14
CID
Redundant Channel Selection:
Enables the redundant Transmit Monitor Output at pins CMI2P/N.
Low: Normal operation (CMIP/N active only)
High: Transmit Monitor Mode (CMIP/N and CMI2P/N active)
LPBK
15
CIT
Analog Loopback Selection:
Low: Normal operation
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
CKMODE
13
CIT
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
Low: Parallel transmit clock is input to the 78P2351.
Float: Parallel transmit clock is input to the 78P2351. Loop-timing
mode enabled.
High: Parallel transmit clock is output from the 78P2351
In SERIAL mode (SDI_PAR low):
Low: Reference clock is synchronous to transmit clock and data. Data
is clocked in with SICKP/N and passed through a FIFO
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
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78P2351-DB-ECLM 功能描述:界面開(kāi)發(fā)工具 78P2351 Demo Brd w/Opticle Module RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
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78P2351-IGT/F 功能描述:接口 - 專(zhuān)用 Single Ch OC-3/STM-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59
78P2351-IGTR 制造商:TERIDIAN 制造商全稱(chēng):TERIDIAN 功能描述:Single Channel OC-3/ STM1-E/ E4 LIU
78P2351-IGTR/F 功能描述:接口 - 專(zhuān)用 Single Ch OC-3/STM-1e/E4 LIU RoHS:否 制造商:Texas Instruments 產(chǎn)品類(lèi)型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59

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