2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號: 78P2351-DB/CMI
廠商: Maxim Integrated Products
文件頁數(shù): 10/42頁
文件大?。?/td> 0K
描述: BOARD DEMO 78P2351 COAX CABLE
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 1
系列: *
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 18 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION (continued)
RECEIVER PINS
NAME
PIN
TYPE
DESCRIPTION
PO0D
PO1D
PO2D
PO3D
41
40
37
36
CO
Receive Data (Parallel Mode) Output:
Recovered receive data de-serialized into four-bit CMOS parallel (nibble)
outputs. The MSB (PO3D) is received first. Active, but undefined during
reset.
Note: During Loss of Signal conditions, data outputs are held low.
POCK
33
CO
Receive (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output generated by
dividing down the recovered receive clock. By default, receive data is
clocked out on the falling edge. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
divided down phase selection of the Rx DLL and output a steady clock.
SODP
SODN
20
21
PO
Receive (Serial Mode) Data Output:
Recovered receive serial NRZ data at LVPECL levels. Active, but undefined
during reset.
Note: During Loss of Signal conditions, data outputs are held at logic 0.
SOCKP
SOCKN
18
19
PO
Receive (Serial Mode) Clock Output:
Recovered receive serial clock. By default, recovered serial NRZ data is
clocked out the falling edge of SOCKP. Active during reset.
Note: During Loss of Signal conditions, the clock will remain on the last
phase selection of the Rx DLL and output a steady clock.
RXP
RXN
90
91
A/
PI
Receiver (CMI or NRZ) Input:
The input is either transformer-coupled to coaxial cable for CMI data or AC-
coupled at LVPECL levels to an optical transceiver module for NRZ data.
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