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參數資料
| 型號： | 7630 |
| 英文描述： | 7630 Group Datasheet Datasheet 840K/JAN.13.99 |
| 中文描述： | 7630組數據表數據表840K/JAN.13.99 |
| 文件頁數： | 23/49頁 |
| 文件大?。?/td> | 840K |
| 代理商： | 7630 |
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22
MITSUBISHI MICROCOMPUTERS
7630 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 20
Timer X bi-phase counter mode operation
(3) Event counter mode
This mode is available with timer X and timer Y.
Count source
The count source for timer X is the input signal to the P1
4
/CNTR
0
pin and for timer Y the input signal to P1
5
/CNTR
1
pin.
Operation
The timer counts down. On a timer underflow, the corresponding
timer interrupt request bit will be set to “1”, the contents of the
corresponding timer latches will be reloaded to the counters and
counting continues. The active edge used for counting can be
selected by the polarity selection bit of the corresponding pin
P1
4
/CNTR
0
or P1
5
/CNTR
1
. These bits are part of TXM (Structure
of Timer X mode register) and TYM (Structure of timer Y mode
register (f is internal system clock)) registers.
(4) Pulse width measurement mode
This mode is available with timer X only.
Count source
The count source is the output of timer X clock divider. The divi-
sion ratio can be selected by the timer Y mode register.
Operation
The timer counts down while the input signal level on
P1
4
/CNTR
0
matches the active polarity selected by the CNTR
0
polarity selection bit of TXM (Structure of Timer X mode regis-
ter). On a timer underflow, the timer X interrupt request bit will be
set to “1”, the contents of the timer latches are reloaded to the
counters and counting continues. When the input level changes
from active polarity (as selected), the CNTR
0
interrupt request bit
will be set to “1.” The measurement result may be obtained by
reading timer X during interrupt service.
(5) Pulse period measurement mode
This mode is available with timer Y only.
Count source
The count source is the output of timer Y clock divider.
Operation
The active edge of input signal to be measured can be selected
by CNTR
1
polarity selection bit (Fig. 18). When this bit is set to
“0”, the time between two consecutive falling edges of the signal
input to P1
5
/CNTR
1
pin will be measured, when the polarity bit is
set to “1”, the time between two consecutive rising edges will be
measured.
The timer counts down. On detection of an active edge of input
signal, the contents of the TY counters will be transferred to tem-
porary registers assigned to the same addresses as TY. At the
same time, the contents of TY latches will be reloaded to the
counters and counting continues. The active edge of input signal
also causes the CNTR
1
interrupt request bit to be set to “1”. The
measurement result may be obtained by reading timer Y during
interrupt service.
(6) H/L pulse width measurement mode
This mode is available with timer Y only.
Count source
The count source is the output of the timer Y’s clock divider.
Operation
This mode measures both the “H” and “L” periods of a signal
input to P1
5
/CNTR
1
pin continuously. On detection of any edge
(rising or falling) of input signal to P1
5
/CNTR
1
pin, the contents of
timer Y counters are stored to temporary registers which are
assigned to the same addresses as timer Y. At the same time,
the contents of timer Y latches are reloaded to the counters and
counting continues. The detection of an edge causes the
CNTR1 interrupt request bit to be set to “1” as well. The result of
measurement may be obtained by reading timer Y during inter-
rupt service. This read access will address the temporary regis-
ters. On a timer underflow, the timer Y interrupt request bit will
be set to “1”, the contents of timer Y latches will be transferred to
the counters and counting continues.
P1
3
/TX
0
input signal
P1
4
/CNTR
0
input signal
TX counter
count direction
down
up
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