參數(shù)資料
型號： 7630
英文描述： 7630 Group Datasheet Datasheet 840K/JAN.13.99
中文描述： 7630組數(shù)據(jù)表數(shù)據(jù)表840K/JAN.13.99
文件頁數(shù)： 16/49頁
文件大小： 840K
代理商： 7630
MITSUBISHI MICROCOMPUTERS
7630 Group
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
.
Table 3: Interrupt vector addresses and priority
Interrupt source
Priority
Vector Address (Note 1)
Interrupt Request Generating
Conditions
Remarks
High
Low
Reset (Note 2)
1
FFFB
16
FFFA
16
At Reset
Non-maskable
Watchdog timer
2
FFF9
16
FFF8
16
At Watchdog timer underflow
Non-maskable
INT
0
3
FFF7
16
FFF6
16
At detection of either rising or falling
edge of INT
0
interrupt
External Interrupt
(active edge selectable)
INT
1
4
FFF5
16
FFF4
16
At detection of either rising or falling
edge of INT
1
interrupt
External Interrupt
(active edge selectable)
CAN
successful
transmit
5
FFF3
16
FFF2
16
At CAN module successful
transmission of message
Valid when CAN module is
activated and request transmit
CAN successful
receive
6
FFF1
16
FFF0
16
At CAN module successful reception
of message
Valid when CAN module is
activated
CAN overrun
7
FFEF
16
FFEE
16
If CAN module receives message
when receive buffers are full.
Valid when CAN module is
activated
CAN error
passive
8
FFED
16
FFEC
16
When CAN module enters into error
passive state
Valid when CAN module is
active
CAN error bus off
9
FFEB
16
FFEA
16
When CAN module enters into bus
off state
Valid when CAN module is
active
CAN wake up
10
FFE9
16
FFE8
16
When CAN module wakes up via
CAN bus
Timer X
11
FFE7
16
FFE6
16
At Timer X underflow or overflow
Timer Y
12
FFE5
16
FFE4
16
At Timer Y underflow
Timer 1
13
FFE3
16
FFE2
16
At Timer 1 underflow
Timer 2
14
FFE1
16
FFE0
16
At Timer 2 underflow
Timer 3
15
FFDF
16
FFDE
16
At Timer 3 underflow
CNTR
0
16
FFDD
16
FFDC
16
At detection of either rising or falling
edge in CNTR
0
input
External Interrupt
(active edge selectable)
CNTR
1
17
FFDB
16
FFDA
16
At detection of either rising or falling
edge in CNTR
1
input
External Interrupt
(active edge selectable)
UART receive
18
FFD9
16
FFD8
16
At completion of UART receive
Valid when UART is selected
UART transmit
19
FFD7
16
FFD6
16
At completion of UART transmit
Valid when UART is selected
UART transmit
buffer empty
20
FFD5
16
FFD4
16
At UART transmit buffer empty
Valid when UART is selected
UART receive
error
21
FFD3
16
FFD2
16
When UART reception error occurs.
Valid when UART is selected
Serial I/O
22
FFD1
16
FFD0
16
At completion of serial I/O data
transmit and receive
Valid when serial I/O is
selected
A-D conversion
23
FFCF
16
FFCE
16
At completion of A-D conversion
Key-on wake-up
24
FFCD
16
FFCC
16
At detection of either rising or falling
edge of P4 input
External Interrupt
(active edge selectable)
BRK instruction
25
FFCB
16
FFCA
16
At BRK instruction execution
Non-maskable
Notes 1: Vector addresses contain interrupt jump destination address
2: Reset function in the same way as an interrupt with the highest priority
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