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參數(shù)資料
| 型號(hào)： | 7536 |
| 英文描述： | Low Quiescent Current LDO, -40C to +125C, 3-SOT-23, T/R |
| 中文描述： | 7536組數(shù)據(jù)表數(shù)據(jù)表660K/SEP.05.00 |
| 文件頁數(shù)： | 34/46頁 |
| 文件大?。?/td> | 660K |
| 代理商： | 7536 |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
7536 Group
MITSUBISHI MICROCOMPUTERS
33
Fig. 40 External circuit of ceramic resonator
Fig. 41 External clock input circuit
Fig. 42 Structure of MISRG
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween X
IN
and X
OUT
.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between X
IN
and X
OUT
since a feed-back resistor exists on-chip.
G
Oscillation control
For the details of the state and release of stop mode and wait mode,
refer to “Stop mode” and “Wait mode” of “FUNCTIONAL DESCRIP-
TION SUPPLEMENT”.
Stop mode
When the STP instruction is executed, the internal clock
φ
stops at
an “H” level and the X
IN
oscillator stops. At this time, timer 1 is set to
“01
16
” and prescaler 12 is set to “FF
16
” when the oscillation
stabilization time set bit after release of the STP instruction is “0”.
On the other hand, timer 1 and prescaler 12 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used.
f(X
IN
)/16 is forcibly connected to the input of prescaler 12.
When an external interrupt is accepted, oscillation is restarted but
the internal clock
φ
remains at “H” until timer 1 underflows. As soon
as timer 1 underflows, the internal clock
φ
is supplied. This is
because when a ceramic oscillator is used, some time is required
until a start of oscillation.
In case oscillation is restarted by reset, no wait time is generated.
So apply an “L” level to the RESET pin while oscillation becomes
stable.
Wait mode
If the WIT instruction is executed, the internal clock
φ
stops at an
“H” level, but the oscillator does not stop. The internal clock
φ
re
starts if a reset occurs or when an interrupt is received.
Since the oscillator does not stop, normal operation can be started
immediately after the clock is restarted.
To ensure that interrupts will be received to release the STP or WIT
state, interrupt enable bits must be set to “1” before the STP or
WIT instruction is executed.
When the STP status is released, prescaler 12 and timer 1 will start
counting with the f(X
IN
)/16, so set the timer 1 interrupt enable bit to
“0” before the STP instruction is executed.
Note
For use with the oscillation stabilization time set bit after release of
the STP instruction set to “1”, set values in timer 1 and prescaler
12 after fully appreciating the oscillation stabilization time of the
oscillator to be used.
Clock mode
Operation is started by a built-in ring oscillator after releasing reset.
A division ratio (1/1,1/2,1/8) is selected by setting bits 7 and 6 of the
CPU mode register after releasing it.
X
IN
C
OUT
C
IN
X
OUT
X
IN
X
OUT
External oscillation
circuit
V
CC
V
SS
Open
MISRG(Address 0038
16
)
b7 b0
Oscillation stabilization time set bit after
release of the STP instruction
0: Set "01
16
" in timer1, and "FF
16
"
in prescaler 12 automatically
1: Not set automatically
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
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PDF描述 |
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