- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375089 > 74VHC161284 (Fairchild Semiconductor Corporation) IEEE 1284 Transceiver PDF資料下載
參數(shù)資料
| 型號： | 74VHC161284 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | IEEE 1284 Transceiver |
| 中文描述： | 符合IEEE 1284收發(fā)器 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 112K |
| 代理商： | 74VHC161284 |
2000 Fairchild Semiconductor Corporation
DS500098
www.fairchildsemi.com
February 1998
Revised July 2000
7
74VHC161284
IEEE 1284 Transceiver
General Description
The VHC161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
±
14 mA). The pull-up and pull-
down series termination resistance of these outputs on the
cable side is optimized to drive an external cable. In addi-
tion, all inputs (except HLH) and outputs on the cable side
contain internal pull-up resistors connected to the V
CC
sup-
ply to provide proper termination and pull-ups for open
drain mode.
Outputs on the Peripheral side are standard LOW-drive
CMOS outputs. The DIR input controls data flow on the
A
1
–A
8
/B
1
–B
8
transceiver pins.
Features
I
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
I
Replaces the function of two (2) 74ACT1284 devices
I
All inputs have hysteresis to provide noise margin
I
B and Y output resistance optimized to drive external
cable
I
B and Y outputs in high impedance mode during power
down
I
Inputs and outputs on cable side have internal pull-up
resistors
I
Flow-through pin configuration allows easy interface
between the Peripheral and Host
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter
“
X
”
to the ordering code.
Logic Symbol
Connection Diagram
Ordering Number
74VHC161284MEA
74VHC161284MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74VHC161284MTDX | IEEE 1284 Transceiver |
| 74VHC161284MTD | Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 74VHC161 | Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 74VHC161M | 4-Bit Binary Counter with Asynchronous Clear |
| 74VHC161MTC | Quadruple 2-Input Positive-NOR Gates 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74VHC161284MEA | 功能描述:總線收發(fā)器 IEEE 16284 Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74VHC161284MEA.DEL | 制造商:Fairchild Semiconductor Corporation 功能描述:IEEE 1284 Transceiver 13TX 12RX 48-Pin SSOP W Rail |
| 74VHC161284MEA_Q | 功能描述:總線收發(fā)器 IEEE 16284 Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74VHC161284MEAX | 功能描述:總線收發(fā)器 IEEE 16284 Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74VHC161284MTD | 功能描述:總線收發(fā)器 IEEE 16284 Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。