參數資料
型號: 74VHC161284MTDX
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: IEEE 1284 Transceiver
中文描述: 13 LINE TRANSCEIVER, PDSO48
封裝: 6.10 MM, MO-153, TSSOP-48
文件頁數: 1/11頁
文件大?。?/td> 112K
代理商: 74VHC161284MTDX
2000 Fairchild Semiconductor Corporation
DS500098
www.fairchildsemi.com
February 1998
Revised July 2000
7
74VHC161284
IEEE 1284 Transceiver
General Description
The VHC161284 contains eight bidirectional data buffers
and eleven control/status buffers to implement a full
IEEE 1284 compliant interface. The device supports the
IEEE 1284 standard and is intended to be used in
Extended Capabilities Port mode (ECP). The pinout allows
for easy connection from the Peripheral (A-side) to the
Host (cable side).
Outputs on the cable side can be configured to be either
open drain or high drive (
±
14 mA). The pull-up and pull-
down series termination resistance of these outputs on the
cable side is optimized to drive an external cable. In addi-
tion, all inputs (except HLH) and outputs on the cable side
contain internal pull-up resistors connected to the V
CC
sup-
ply to provide proper termination and pull-ups for open
drain mode.
Outputs on the Peripheral side are standard LOW-drive
CMOS outputs. The DIR input controls data flow on the
A
1
–A
8
/B
1
–B
8
transceiver pins.
Features
I
Supports IEEE 1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
I
Replaces the function of two (2) 74ACT1284 devices
I
All inputs have hysteresis to provide noise margin
I
B and Y output resistance optimized to drive external
cable
I
B and Y outputs in high impedance mode during power
down
I
Inputs and outputs on cable side have internal pull-up
resistors
I
Flow-through pin configuration allows easy interface
between the Peripheral and Host
Ordering Code:
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter
X
to the ordering code.
Logic Symbol
Connection Diagram
Ordering Number
74VHC161284MEA
74VHC161284MTD
Package Number
MS48A
MTD48
Package Description
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
相關PDF資料
PDF描述
74VHC161284MTD Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
74VHC161 Quadruple 2-Input Positive-NAND Gates 14-TSSOP -40 to 85
74VHC161M 4-Bit Binary Counter with Asynchronous Clear
74VHC161MTC Quadruple 2-Input Positive-NOR Gates 14-SOIC -40 to 85
74VHC161N Quadruple 2-Input Positive-NOR Gates 14-SOIC -40 to 85
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