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參數(shù)資料
| 型號(hào)： | 74VCX16835MTD |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs |
| 中文描述： | ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 6.10 MM, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 77K |
| 代理商： | 74VCX16835MTD |
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7
AC Electrical Characteristics
(Note 10)
Note 10:
For CL
=
50pF, add approximately 300ps to the AC maximum specification.
Note 11:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
AC Electrical Characteristics Over Load
(Note 12)
Note 12:
This parameter is guaranteed by characterization but not tested.
Note 13:
SSO = Simultaneous Switching Output. Any output combination of LOW-to-HIGH and/or HIGH-to-LOW transition.
Dynamic Switching Characteristics
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C, C
L
=
30 pF, R
L
=
500
V
CC
=
3.3V
±
0.3V
V
CC
=
2.5
±
0.2V
Min
Max
Min
250
200
Units
V
CC
=
1.8
±
0.15V
Min
100
Max
Max
f
MAX
t
PHL
,
t
PLH
t
PHL
,
t
PLH
t
PHL
,
t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
S
t
H
t
W
t
OSHL
t
OSLH
Maximum Clock Frequency
Propagation Delay
MHz
0.6
3.3
0.8
4.2
1.5
8.4
ns
Bus to Bus
Propagation Delay
Clock to Bus
1.4
4.2
1.5
5.2
2.0
9.2
ns
Propagation Delay
LE to Bus
Output Enable Time
0.6
3.8
0.8
4.9
1.5
9.8
ns
0.6
3.8
0.8
4.9
1.5
9.8
ns
Output Disable Time
Setup Time
Hold Time
0.6
1.5
0.7
3.9
0.8
1.5
0.7
4.5
1.5
2.5
1.0
7.6
ns
ns
ns
Pulse Width
Output to Output Skew
(Note 11)
1.5
1.5
4.0
ns
0.5
0.5
0.75
ns
Symbol
Parameter
T
A
=
0
°
C to
+
85
°
C, R
L
=
500
V
CC
=
3.3V
±
0.15V
C
L
=
0 pF
Min
Max
0.7
2.1
1.5
3.0
Units
C
L
=
50 pF
Min
1.0
1.7
Max
3.6
4.5
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PHL
, t
PLH
t
PZL
, t
PZH
t
PLZ
, t
PHZ
t
PHL
, t
PLH
t
S
t
H
Prop Delay Bus to Bus
Prop Delay Clock to Bus
ns
ns
Prop Delay LE to Bus
Output Enable Time
Output Disable Time
0.7
0.7
0.7
2.6
2.6
2.7
1.0
1.0
1.0
4.1
4.1
4.2
ns
ns
ns
SSO Prop Delay Clock to Bus (Note 13)
Setup Time
Hold Time
1.5
1.5
0.7
3.3
ns
ns
ns
1.5
0.7
Symbol
Parameter
Conditions
V
CC
(V)
1.8
2.5
3.3
T
A
=+
25
°
C
Typical
0.35
0.7
0.9
0.35
0.7
0.9
1.3
1.7
2.0
Units
V
OLP
Quiet Output Dynamic Peak V
OL
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
V
V
OLV
Quiet Output Dynamic Valley V
OL
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
1.8
2.5
3.3
V
V
OHV
Quiet Output Dynamic Valley V
OH
C
L
=
30 pF, V
IH
=
V
CC
, V
IL
=
0V
1.8
2.5
3.3
V
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| 74VCX16835MTD_Q | 功能描述:總線收發(fā)器 18-Bit Univ Bus Drv RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74VCX16835MTDX | 功能描述:總線收發(fā)器 18-Bit Univ Bus Drv RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74VCX16838 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 74VCX16838_05 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Low Voltage 16-Bit Selectable Register/Buffer with 3.6V Tolerant Inputs and Outputs |
| 74VCX16838_ZAA31162 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
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