- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382823 > 74LVTH543MTC (FAIRCHILD SEMICONDUCTOR CORP) Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LVTH543MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 中文描述： | LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | 4.40 MM, MO-153, TSSOP-24 |
| 文件頁(yè)數(shù)： | 2/7頁(yè) |
| 文件大?。?/td> | 66K |
| 代理商： | 74LVTH543MTC |
www.fairchildsemi.com
2
7
Logic Symbols
IEEE/IEC
Functional Description
The LVTH543 contains two sets of D-type latches, with
separate input and output controls for each. For data flow
from A to B, for example, the A to B Enable (CEAB) input
must be LOW in order to enter data from the A Port or take
data from the B Port as indicated in the Data I/O Control
Table. With CEAB LOW, a low signal on (LEAB) input
makes the A to B latches transparent; a subsequent LOW-
to-HIGH transition of the LEAB line puts the A latches in
the storage mode and their outputs no longer change with
the A inputs. With CEAB and OEAB both LOW, the B out-
put buffers are active and reflect the data present on the
output of the A latches. Control of data flow from B to A is
similar, but using the CEBA, LEBA and OEBA.
Data I/O Control Table
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
Note:
A-to-B data flow shown; B-to-A flow control is the same, except
using CEBA, LEBA, and OEBA.
Logic Diagram
Please not that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs
Latch Status
Output
CEAB
LEAB
OEAB
Buffers
H
X
X
Latched
High Z
X
H
X
Latched
—
L
L
X
Transparent
—
X
X
H
—
High Z
L
X
L
—
Driving
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVTH573MTCX_NL | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 74LVTH573 | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 74LVTH573MSA | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 74LVTH573MSAX | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 74LVTH573MTC | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH543MTCX | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH543WM | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH543WMX | 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| 74LVTH573MSA | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH573MSA_Q | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類(lèi)型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。