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參數(shù)資料
| 型號： | 74LVTH573MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 中文描述： | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 4.40 MM, MO-153AC, TSSOP-20 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 107K |
| 代理商： | 74LVTH573MTC |
2005 Fairchild Semiconductor Corporation
DS012450
www.fairchildsemi.com
March 1999
Revised March 2005
7
74LVT573
74LVTH573
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT573 and LVTH573 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is low, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in the high impedance state.
The LVTH573 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT573 and LVTH573
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining a low power dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH573),
also available without bushold feature (74LVT573)
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink 32 mA/ 64 mA
I
Functionally compatible with the 74 series 573
I
Latch-up performance exceeds 500 mA
I
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Order Number
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
Package Description
74LVT573WM
74LVT573SJ
74LVT573MSA
74LVT573MTC
74LVT573MTCX_NL
(Note 1)
74LVTH573WM
74LVTH573SJ
74LVTH573MSA
74LVTH573MTC
74LVTH573MTCX_NL
(Note 1)
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
M20B
M20D
MSA20
MTC20
MTC20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVTH573MTCX | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 74LVTH573SJ | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 74LVTH573SJX | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
| 74LVTH573WM | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 74LVTH573WMX | Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH573MTCX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH573SJ | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH573SJ_Q | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH573SJX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH573WM | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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