參數(shù)資料
型號(hào): 74LVTH543
廠商: Fairchild Semiconductor Corporation
英文描述: Low Voltage Octal Registered Transceiver with 3-STATE Outputs
中文描述: 低壓八路注冊(cè)收發(fā)器三態(tài)輸出
文件頁(yè)數(shù): 5/7頁(yè)
文件大?。?/td> 66K
代理商: 74LVTH543
5
www.fairchildsemi.com
7
AC Electrical Characteristics
Note 8:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
(Note 9)
Note 9:
Capacitance is measured at frequency f
=
1 MHz, per MIL-STD-883B, Method 3012.
Symbol
Parameter
T
A
=
40
°
C to
+
85
°
C
Units
C
L
=
50 pF, R
L
=
500
V
CC
=
3.3V
±
0.3V
V
CC
=
2.7V
Min
Max
Min
Max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
1.3
4.4
1.3
4.8
ns
Data to Outputs
1.3
4.6
1.3
5.2
Propagation Delay
1.3
5.4
1.3
6.4
ns
LE to A or B
1.3
5.8
1.3
6.6
Output Enable Time
1.1
5.5
1.1
6.3
ns
OE to A or B
1.1
6.1
1.1
7.2
Output Disable Time
2.0
5.7
2.0
5.9
ns
OE to A or B
2.0
5.3
2.0
5.9
Output Enable Time
1.3
5.9
1.3
6.8
ns
CE to A or B
1.3
6.2
1.3
7.4
Output Disable Time
2.1
5.8
2.1
6.1
ns
CE to A or B
1.6
5.4
1.6
5.9
t
W
Pulse Duration
LE LOW
3.3
3.3
ns
t
S
Setup Time
A or B before LE, Data HIGH
0.4
0.4
ns
A or B before LE, Data LOW
1.0
1.5
A or B before CE, Data HIGH
0.2
0.2
A or B before CE, Data LOW
0.7
1.2
t
H
Hold Time
A or B before LE, Data HIGH
1.5
0.6
ns
A or B before LE, Data LOW
1.3
1.5
A or B before CE, Data HIGH
1.6
0.5
A or B before CE, Data LOW
1.4
1.6
t
OSHL
t
OSLH
Output to Output Skew (Note 8)
1.0
1.0
ns
1.0
1.0
Symbol
Parameter
Conditions
Typical
Units
C
IN
C
I/O
Input Capacitance
Input/Output Capacitance
V
CC
=
0V, V
I
=
0V or V
CC
V
CC
=
3.0V, V
O
=
0V or V
CC
4
8
pF
pF
相關(guān)PDF資料
PDF描述
74LVTH543MTC Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85
74LVTH573MTCX_NL Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVTH573 Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85
74LVTH573MSA Low Voltage Octal Transparent Latch with 3-STATE Outputs
74LVTH573MSAX Quadruple Positive-OR Gates With Schmitt-Trigger Inputs 14-SOIC -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74LVTH543_ZBB3026B WAF 制造商:Fairchild Semiconductor Corporation 功能描述:
74LVTH543MTC 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVTH543MTCX 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVTH543WM 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVTH543WMX 功能描述:總線收發(fā)器 Octal Reg Trans RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel