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參數(shù)資料
| 型號： | 74LVTH373MTC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-SO -40 to 85 |
| 中文描述： | LVT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20 |
| 封裝： | 4.40 MM, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 67K |
| 代理商： | 74LVTH373MTC |
1999 Fairchild Semiconductor Corporation
DS012015
www.fairchildsemi.com
September 1999
Revised October 1999
7
74LVT373 74LVTH373
Low Voltage Octal Transparent Latch
with 3-STATE Outputs
General Description
The LVT373 and LVTH373 consist of eight latches with
3-STATE outputs for bus organized system applications.
The latches appear transparent to the data when Latch
Enable (LE) is HIGH. When LE is LOW, the data satisfying
the input timing requirements is latched. Data appears on
the bus when the Output Enable (OE) is LOW. When OE is
HIGH, the bus output is in a high impedance state.
The LVTH373 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These octal latches are designed for low-voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT373 and LVTH373
are fabricated with an advanced BiCMOS technology to
achieve high speed operation similar to 5V ABT while
maintaining low power dissipation.
Features
I
Input and output interface capability to systems at
5V V
CC
I
Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH373), also
available without bushold feature (74LVT373).
I
Live insertion/extraction permitted
I
Power Up/Down high impedance provides glitch-free
bus loading
I
Outputs source/sink
32 mA/
+
64 mA
I
Functionally compatible with the 74 series 373
Ordering Code:
Logic Symbols
IEEE/IEC
Order Number
74LVT373WM
74LVT373SJ
74LVT373MTC
74LVTH373WM
74LVTH373SJ
74LVTH373MTC
Package Number
M20B
M20D
MTC20
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LVTH373SJ | Low Voltage Octal Transparent Latch with 3-STATE Outputs |
| 74LVTH373WM | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
| 74LVTH543WM | Low Voltage Octal Registered Transceiver with 3-STATE Outputs |
| 74LVTH543 | Low Voltage Octal Registered Transceiver with 3-STATE Outputs |
| 74LVTH543MTC | Quadruple Positive-NOR Gates With Schmitt-Trigger Inputs 14-TSSOP -40 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVTH373MTCX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH373MTCX_NL | 功能描述:閉鎖 LV OCTAL TRANSP LATCH BH RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH373SJ | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH373SJ_Q | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| 74LVTH373SJX | 功能描述:閉鎖 Octal Trans Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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