參數(shù)資料
型號: 74LVTH162373MEX
廠商: Fairchild Semiconductor
文件頁數(shù): 2/7頁
文件大小: 0K
描述: IC LATCH TRANSP 16BIT 3ST 48SSOP
產(chǎn)品變化通告: Die Material/Mold Compound Change 10/Sept/2008
標準包裝: 1,000
系列: 74LVTH
邏輯類型: D 型透明鎖存器
電路: 8:8
輸出類型: 三態(tài)
電源電壓: 2.7 V ~ 3.6 V
獨立電路: 2
延遲時間 - 傳輸: 1.4ns
輸出電流高,低: 12mA,12mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 48-SSOP
包裝: 帶卷 (TR)
www.fairchildsemi.com
2
74L
VTH162373
Connection Diagram
Pin Descriptions
Truth Tables
H
HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
HIGH Impedance
Oo
Previous output prior to HIGH-to-LOW transition of LE
Functional Description
The LVTH162373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each
byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation.
The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the
latches. In this condition the latches are transparent, i.e, a latch output will change states each time its D input changes.
When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW
transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the
standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but
this does not interfere with entering new data into the latches.
Pin Names
Description
OEn
Output Enable Input (Active LOW)
LEn
Latch Enable Input
I0–I15
Inputs
O0–O15
3-STATE Outputs
Inputs
Outputs
LE1
OE1
I0–I7
O0–O7
X
H
X
Z
H
L
H
L
H
L
X
Oo
Inputs
Outputs
LE2
OE2
I8–I15
O8–O15
X
H
X
Z
H
L
H
L
H
L
X
Oo
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