參數(shù)資料
型號： 74LVC86AN
廠商： NXP SEMICONDUCTORS
元件分類： 通用總線功能
英文描述： Quad 2-input exclusive OR gate
中文描述： LVC/LCX/Z SERIES, QUAD 2-INPUT XOR GATE, PDIP14
文件頁數(shù)： 4/10頁
文件大?。?/td> 102K
代理商： 74LVC86AN
Philips Semiconductors
Product specification
74LVC86A
Quad 2-input exclusive OR gate
1998 Apr 28
4
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40
°
C to +85
°
C
UNIT
MIN
TYP
1
MAX
V
IH
HIGH level Input voltage
V
CC
= 1.2V
V
CC
V
V
CC
= 2.7 to 3.6V
2.0
V
IL
LOW level Input voltage
V
CC
= 1.2V
GND
V
V
CC
= 2.7 to 3.6V
0.8
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= –12mA
V
CC
0.5
V
OH
HIGH level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= –100
μ
A
V
CC
0.2
V
CC
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –18mA
V
CC
0.6
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= –24mA
V
CC
0.8
V
CC
= 2.7V; V
I
= V
IH
or V
IL
; I
O
= 12mA
0.40
V
OL
LOW level output voltage
V
CC
= 3.0V; V
I
= V
IH
or V
IL
; I
O
= 100
μ
A
0.20
V
V
CC
= 3.0V; V
I
= V
IH
or V
IL;
I
O
= 24mA
0.55
I
I
Input leakage current
V
CC
= 3 6V; V = 5 5V or GND
I
= 5.5V or GND
0 1
0.1
5
μ
A
I
CC
Quiescent supply current
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
0.1
10
μ
A
I
CC
Additional quiescent supply current
per input pin
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V; I
O
= 0
5
500
μ
A
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
2.5 ns; C
L
= 50 pF; R
L
= 500 ; T
amb
= –40 C to +85 C
LIMITS
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
MIN
TYP
1
V
CC
= 2.7V
TYP
1
V
CC
= 1.2V
TYP
UNIT
MAX
MIN
MAX
t
PHL
/
t
PLH
Propagation delay
nA, nB to nY
Figures 1, 2
1.5
3.0
5
1.5
3.4
5.8
11
ns
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
V
M
= 0.5 V
CC
at V
CC
< 2.7 V
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7 V
V
I
nA, nB INPUT
GND
V
OH
nY OUTPUT
V
OL
V
M
t
PHL
t
PLH
V
M
SV00377
Figure 1. Input (nA, nB) to output (nY) propagation delays
TEST CIRCUIT
PULSE
GENERATOR
V
I
R
T
D.U.T.
V
O
C
L
50pF
S
1
2
Open
GND
V
CC
500
500
V
CC
V
I
2.7V
V
CC
2.7V
2.7V – 3.6V
Test
S
1
t
PLH
/t
PHL
Open
V
CC
SY00077
Figure 2. Load circuitry for switching times.
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