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參數(shù)資料
| 型號(hào)： | 74LVC823A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 9-bit D-type flip-flop with 5-volt tolerant inputs/outputs;positive-edge trigger(3-State)(帶5V輸入/輸出容限的上升沿觸發(fā)的9位D觸發(fā)器（三態(tài)）) |
| 中文描述： | 9位D型觸發(fā)器5伏容限輸入/輸出;積極邊緣觸發(fā)（3態(tài)）（帶5V的輸入/輸出容限的上升沿觸發(fā)的9位?觸發(fā)器（三態(tài)）） |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 106K |
| 代理商： | 74LVC823A |
Philips Semiconductors
Product specification
74LVC823A
9-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
2
1998 Sep 24
853-2124 20078
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Supply voltage range of 2.7V to 3.6V
Complies with JEDEC standard no. 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
9-bit positive edge-triggered register
Independent register and 3-State buffer operation
Flow-through pin-out architecture
DESCRIPTION
The 74LVC823A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC823A is a 9-bit D-type flip-flop with common clock (CP),
Clock Enable (CE), Master Reset (MR) and 3-State outputs for
bus-oriented applications.
The nine flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition provided CE is LOW. When CE is HIGH the flip-flops
hold their data.
A LOW on MR resets all flip-flops.
When OE is LOW, the contents of the nine flip-flops is available at
the outputs. When OE is HIGH, the outputs go to the high
impedance OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
PLH
/t
Propagation delay
CP to Q
n
Propagation delay
MR to Q
n
C
= 50 pF;
L
V
CC
= 3.3 V
5.1
ns
5.2
ns
f
max
Maximum clock frequency
C
L
= 50 pF;
V
CC
= 3.3 V
150
MHz
C
I
Input capacitance
5.0
pF
C
PD
Power dissipation capacitance per
flip-flop
Notes 1 and 2
27
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
×
V
CC2
×
f
i
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDERING CODE
PKG. DWG. #
24-Pin Plastic SO
–40
°
C to +85
°
C
74LVC823A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74LVC823A DB
SOT340-1
24-Pin Plastic TSSOP Type I
74LVC823A PW
SOT355-1
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