參數(shù)資料
型號(hào)： 74LVC646A
廠商： NXP Semiconductors N.V.
英文描述： Octal bus transceiver/register (3-State)(八通道總線收發(fā)器/寄存器（三態(tài)）)
中文描述： 八路總線收發(fā)器/寄存器（3態(tài)）（八通道總線收發(fā)器/寄存器（三態(tài)））
文件頁(yè)數(shù)： 2/16頁(yè)
文件大小： 138K
代理商： 74LVC646A
Philips Semiconductors
Product specification
74LVC646A
Octal bus transceiver/register (3-State)
2
1998 Jul 29
853-2105 19803
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Flow-through pin-out architecture
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC646A is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC646A consist of non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal
registers, as the appropriate clock (CPAB or CPBA) goes to a HIGH
logic level. Output enable (OE) and direction (DIR) inputs are
provided to control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in either the
‘A’ or ‘B’ register, or in both. The select source inputs (SAB and
SBA) can multiplex stored and real-time (transparent mode) data.
The direction (DIR) input determines which bus will receive data
when OE is active (LOW). In the isolation mode (OE = HIGH), ‘A’
data may be stored in the ‘B’ register and/or ‘B’ data may be stored
in the ‘A’ register.
When an output function is disabled, the input function is still
enabled and may be used to store and transmit data. Only one of
the two buses, ‘A’ or ‘B’ may be driven at a time.
The ‘646A’ is functionally identical to the ‘648A’ but has non-inverting
data paths.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
An to Yn
Maximum clock frequency
Input capacitance
Input/output capacitance
Power dissipation capacitance per gate
C
L
= 50pF
V
CC
= 3.3V
3.9
250
5.0
10
26
ns
f
max
C
I
C
I/O
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
Σ
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
Σ
(C
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
MHz
pF
pF
pF
Notes 1, 2
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°
C to +85
°
C
74LVC646A D
74LVC646A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74LVC646A DB
74LVC646A DB
SOT340-1
24-Pin Plastic TSSOP Type I
74LVC646A PW
7LVC646APW DH
SOT355-1
相關(guān)PDF資料
PDF描述
74LVC652 Octal bus transceiver/register with dual enable (3-State)(帶雙使能的八總線收發(fā)器/寄存器（三態(tài)）)
74LVC652DB Octal transceiver/register with dual enable 3-State
74LVC652D Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SSOP -40 to 85
74LVC652PW Octal transceiver/register with dual enable 3-State
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
74LVC646AD 功能描述:總線收發(fā)器 OCTAL BUS INTERFACE TRANS/REG RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVC646AD,112 功能描述:總線收發(fā)器 OCTAL BUS INTERFACE RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVC646AD,118 功能描述:總線收發(fā)器 OCTAL BUS INTERFACE RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVC646ADB 功能描述:總線收發(fā)器 OCTAL BUS INTERFACE TRANS/REG RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
74LVC646ADB,112 功能描述:總線收發(fā)器 OCTAL BUS INTERFACE RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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