參數(shù)資料
型號(hào): 74LVC573
廠商: NXP Semiconductors N.V.
英文描述: Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State
中文描述: 八路D型透明鎖存5伏/輸出三態(tài)耐壓輸入
文件頁(yè)數(shù): 7/12頁(yè)
文件大?。?/td> 102K
代理商: 74LVC573
Philips Semiconductors
Product specification
74LVC573A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
1998 Jul 29
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V; V
X
= V
OL
+ 0.1 V
CC
at V
CC
V
Y
= V
OH
–0.3V at V
CC
2.7V; V
Y
= V
OH
– 0.1 V
CC
at V
CC
2.7V; V
M
= 0.5 V
CC
at V
CC
2.7V.
2.7V
2.7V
SY00041
INPUT
V
M
t
PHL
t
PLH
V
OL
V
I
V
M
GND
V
OH
OUTPUT
Waveform 1. Input (D
n
) to output (Qn) propagation delays.
t
w
t
PHL
t
PLH
LE INPUT
Qn OUTPUT
V
M
V
M
SA00388
V
I
GND
V
OH
V
OL
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Q
n
) propagation delays
t
PLZ
t
PZL
V
I
nOE INPUT
GND
V
CC
Q
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
Q
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
outputs
enabled
outputs
disabled
t
PHZ
V
M
V
M
V
M
t
PZH
V
X
V
Y
SW00207
Waveform 3. 3-State enable and disable times.
ééé
ééééééééé
ééééééééé
ééééééééé
th
th
V
M
Dn
INPUT
V
M
LE
INPUT
GND
t
SU
NOTE:
The shaded areas indicate when the input is permitted to change
for predictable output performance.
SW00073
t
SU
V
I
GND
V
I
Waveform 4. Data setup and hold times for the D
n
input to the
LE input.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
IN
D.U.T.
V
OUT
C
L
V
CC
R
L
=500
SWITCH POSITION
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
SWITCH
Open
2
V
CC
GND
Test Circuit for 3-State Outputs
Open
GND
S
1
2
V
CC
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitance
R
T
=Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
2.7V
2.7 – 3.6V
V
IN
V
CC
2.7V
SW00047
R
L
=500
Waveform 5. Load circuitry for switching times.
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