參數(shù)資料
型號: 74LVC4066
廠商: NXP Semiconductors N.V.
英文描述: Quad bilateral switches
中文描述: 四雙邊開關(guān)
文件頁數(shù): 2/23頁
文件大?。?/td> 133K
代理商: 74LVC4066
2003 Aug 12
2
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
FEATURES
Very low ON resistance:
– 7.5
(typical) at V
CC
= 2.7 V
– 6.5
(typical) at V
CC
= 3.3 V
– 6
(typical) at V
CC
= 5 V.
ESD protection:
– HBM EIA/JESD22-A114-A Exceeds 2000 V
– MM EIA/JESD22-A115-A Exceeds 200 V.
High noise immunity
CMOS low power consumption
Latch up performance exceeds 250 mA
Complies with JEDEC standard no. 8-1A
Direct interface TTL-levels.
DESCRIPTION
The 74LVC4066 is a high-speed Si-gate CMOS device.
The 74LVC4066 has four independent analog switches.
Each switch has two input/output terminals (nY and nZ)
and an active HIGH enable input (nE). When nE is LOW,
the analog switch is turned off.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
2.5 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
×
N + ((C
L
+ C
S
)
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
C
S
= switch capacitance.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PZH
/t
PZL
turn-on time E to V
os
C
L
= 50 pF; R
L
= 500
; V
CC
= 3 V
C
L
= 50 pF; R
L
= 500
; V
CC
= 5 V
C
L
= 50 pF; R
L
= 500
; V
CC
= 3 V
C
L
= 50 pF; R
L
= 500
; V
CC
= 5 V
V
CC
= 3 V
V
CC
= 3.3 V; notes 1 and 2
OFF-state
ON-state
2.5
1.9
3.4
2.5
3.5
12.5
8.0
14.0
ns
ns
ns
ns
pF
pF
pF
pF
t
PHZ
/t
PLZ
turn-off time E to V
os
C
I
C
PD
C
S
input capacitance
power dissipation capacitance
switch capacitance
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