參數(shù)資料
型號(hào)： 74LVC4066
廠商： NXP Semiconductors N.V.
英文描述： Quad bilateral switches
中文描述： 四雙邊開(kāi)關(guān)
文件頁(yè)數(shù)： 16/23頁(yè)
文件大?。?/td> 133K
代理商： 74LVC4066
2003 Aug 12
16
Philips Semiconductors
Product specification
Quad bilateral switches
74LVC4066
Notes
1.
2.
3.
Adjust f
in
voltage to obtain 0 dBm level at output. Increase f
in
frequency until dB meter reads
3 dB.
Adjust f
in
voltage to obtain 0 dBm level at input.
Guaranteed by design.
α
OFF(feedthru)
switch OFF signal feed-through
attenuation
R
L
= 600
; C
L
= 50 pF;
f
in
= 1 MHz; see Fig.19; note 2
1.65
2.3
3
4.5
1.65
2.3
3
4.5
1.65
2.3
3
4.5
1.65
2.3
3
4.5
1.65
2.3
3
4.5
2.5
3.3
5.0
3.3
5.5
46
46
46
46
42
42
42
42
69
87
156
302
58
58
58
58
58
58
58
58
11.0
12.5
15.6
0.8
1.2
dB
dB
dB
dB
dB
dB
dB
dB
mV
mV
mV
mV
dB
dB
dB
dB
dB
dB
dB
dB
pF
pF
pF
pC
pC
R
L
= 50
; C
L
= 5 pF; f
in
= 1 MHz;
see Fig.19; note 2
α
ct(E-Y/Z)
crosstalk between control input
to signal output
R
L
= 600
; C
L
= 50 pF;
f
in
= 1 MHz; t
r
= t
f
= 2 ns; see
Fig.20
α
ct(S)
crosstalk between switches)
R
L
= 600
; C
L
= 50 pF;
f
in
= 1 MHz; see Fig.21
R
L
= 50
; C
L
= 5 pF; f
in
= 1 MHz;
see Fig.21
C
PD
power dissipation capacitance
f
in
= 10 MHz
Q
charge injection
C
L
= 0.1 nF; V
gen
= 0 V; R
gen
= 0
;
f = 1 MHz; R
L
= 1 M
; see Fig.22;
note 3
SYMBOL
PARAMETER
TEST CONDITIONS
V
CC
(V)
TYPICAL
UNIT
handbook, full pagewidth
MNA669
0.1
μ
F
RL
VO
1/2VCC
CLdB
Z/Y
Y/Z
channel
ON
E
VIH
fin
50
Fig.17 Test circuit for measuring the frequency response when switch is ON.
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