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參數(shù)資料
| 型號： | 74LVC109 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | 雙JK觸發(fā)器設(shè)置和復(fù)位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 103K |
| 代理商： | 74LVC109 |
Philips Semiconductors
Product specification
74LVC109
Dual JK flip-flop with set and reset; positive-edge trigger
2
1998 Apr 28
853–1947 19308
FEATURES
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output capability: standard
I
CC
category: flip-flops
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LVC109 is a dual positive-edge triggered JK-type flip-flop
featuring individual J, K inputs, clock (CP) inputs, set (S
D
) and reset
(R
D
) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K inputs must
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
2.5 ns
SYMBOL
Propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
f
max
Maximum clock frequency
C
I
Input capacitance
C
PD
Power dissipation capacitance per flip-flop
NOTE:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
= C
×
V
CC2
×
f
Σ
(C
L
×
V
CC2
×
f
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
C
L
= 50 pF;
V
CC
= 3.3 V
4.0
4.5
4.5
ns
250
MHz
5.0
pF
V
I
= GND to V
CC1
27
pF
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic SO
74LVC109 D
74LVC109 D
SOT109-1
16-Pin Plastic SSOP Type II
74LVC109 DB
74LVC109 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LVC109 PW
74LVC109PW DH
SOT403-1
PIN CONFIGURATION
SV00517
1RD
1K
1CP
1SD
VCC
2RD
2J
2K
2CP
2SD
2Q
2Q
1J
1Q
1Q
GND
14
13
12
11
10
9
8
1
2
3
4
5
6
7
16
15
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 15
1R
D
, 2R
D
Asynchronous reset input
(active LOW)
Synchronous inputs;
flip-flops 1 and 2
Clock input
(LOW-to-HIGH, edge-triggered)
Asynchronous set inputs
(active LOW)
True flip-flop outputs
2, 14, 3, 13
1J, 2J, 1K, 2K
4, 12
1CP, 2CP
5, 11
1S
D,
2S
D
6, 10
1Q, 2Q
7, 9
1Q, 2Q
Complement flip-flop outputs
8
GND
Ground (O V)
16
V
CC
Positive supply voltage
相關(guān)PDF資料 |
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|---|---|
| 74LVC109PWDH | Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LVC10A | Octal Bus Transceivers With 3-State Outputs 20-TSSOP -40 to 85 |
| 74LVC10APWDH | Triple 3-input NAND gate |
| 74LVC10 | Triple 3-input NAND gate |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LVC109ASO | 制造商:Integrated Device Technology Inc 功能描述:74LVC109ASO - Bulk |
| 74LVC109AXTDC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| 74LVC109AXTPY | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Integrated Device Technology Inc 功能描述: |
| 74LVC109D | 制造商:NXP Semiconductors 功能描述:Flip Flop JK# -Type Pos-Edge 2-Element 16-Pin SO |
| 74LVC109D,112 | 功能描述:觸發(fā)器 3.3V DUAL JK SET RESET POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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