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參數(shù)資料
| 型號(hào)： | 74LV595PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | 8-bit serial-in/serial or parallel-out shift register with output latches 3-State |
| 中文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | 74LV595PWDH |
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Philips Semiconductors
Product specification
74LV595
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
2
1998 Apr 20
853-1987 19255
FEATURES
Optimized for Low Voltage applications: 1.0V to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce) < 0.8V at V
CC
= 3.3V,
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot) > 2V at V
CC
= 3.3V,
T
amb
= 25
°
C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-State outputs
Shift register with direct clear
Output capability:
– parallel outputs; bus driver
– serial output; standard
I
CC
category: MSI
APPLICATIONS
Serial-to-parallel data conversion
Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT595.
The74LV595 is an 8-stage serial shift register with a storage register
and 3-State outputs. The shift register and storage register have
separate clocks.
Data is shifted on the positive-going transitions of the SH
CP
input.
The data in each register is transferred to the storage register on a
positive-going transition of the ST
CP
input. If both clocks are
connected together, the shift register will always be one clock pulse
ahead of the storage register.
The shift register has a serial input (D
S
) and a serial standard output
(Q
7’
) all for cascading. It is also provided with asynchronous reset
(active LOW) for all 8 shift register stages. The storage register has
8 parallel 3-State bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is
LOW.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
SH
CP
to Q
7’
ST
to Q
7’
MR to Q
7’
Maximum clock frequency SH
CP
, ST
CP
Input capacitance
C
L
= 15pF
V
CC
= 3.3V
15
16
14
ns
f
max
C
I
77
MHz
3.5
pF
C
PD
Power dissipation capacitance per gate
V
CC
= 3.3V
Notes 1
and
2
115
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
–40
°
C to +125
°
C
74LV595 N
74LV595 N
SOT38-4
16-Pin Plastic SO
74LV595 D
74LV595 D
SOT109-1
16-Pin Plastic SSOP Type II
74LV595 DB
74LV595 DB
SOT338-1
16-Pin Plastic TSSOP Type I
74LV595 PW
74LV595PW DH
SOT403-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV595 | 8-bit serial-in/serial or parallel-out shift register with output latches (3-State)(帶輸出鎖存的8位串聯(lián)輸入/串聯(lián)或并聯(lián)輸出移位寄存器（三態(tài)）) |
| 74LV688DB-T | Identity Comparator |
| 74LV688D-T | 1024K, 128K X 8, 2.5V SER EE, -40C to +85C, 8-PDIP, TUBE |
| 74LV688PW-T | Identity Comparator |
| 74LV688PWDH | 8-bit magnitude comparator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV595PW-T | 制造商:NXP Semiconductors 功能描述:Shift Register Single 8-Bit Serial to Serial/Parallel 16-Pin TSSOP T/R |
| 74LV688 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit magnitude comparator |
| 74LV688D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit magnitude comparator |
| 74LV688DB | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:8-bit magnitude comparator |
| 74LV688DB-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Identity Comparator |
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