參數(shù)資料
型號: 74LV595
廠商: NXP Semiconductors N.V.
英文描述: 8-bit serial-in/serial or parallel-out shift register with output latches (3-State)(帶輸出鎖存的8位串聯(lián)輸入/串聯(lián)或并聯(lián)輸出移位寄存器(三態(tài)))
中文描述: 8位serial-in/serial或并行輸出的移位寄存器的輸出鎖存器(3態(tài))(帶輸出鎖存的8位串聯(lián)輸入/串聯(lián)或并聯(lián)輸出移位寄存器(三態(tài)))
文件頁數(shù): 8/16頁
文件大?。?/td> 137K
代理商: 74LV595
Philips Semiconductors
Product specification
74LV595
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
1998 Apr 20
8
AC CHARACTERISTICS (Continued)
GND = 0V; t
r
= t
f
2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
1
10
8
6
2
7
5
4
2
10
8
6
2
40
14
10
8
2
40
14
10
8
2
–10
–4
–3
–2
2
–35
–12
–9
–7
2
40
58
70
2
LIMITS
–40 to +125
°
C
MIN
41
30
24
41
30
24
41
30
24
31
23
18
31
23
18
5
5
5
5
5
5
12
16
20
UNIT
V
CC
(V)
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
MIN
34
25
20
34
25
20
34
25
20
26
19
15
26
19
15
5
5
5
5
5
5
14
19
24
MAX
MAX
Shift clock pulse
width HIGH or LOW
t
W
Figure 1
ns
Storage clock pulse
width HIGH or LOW
t
W
Figure 2
ns
Master reset pulse
width LOW
t
W
Figure 5
ns
t
su
Set-up time
D
S
to SH
CP
Figure 4
ns
t
su
Set-up time
SH
CP
to ST
CP
Figure 2
ns
t
h
Hold time
D
S
to SH
CP
Figure 4
ns
t
rem
Removal time
MR to SH
CP
Figure 5
ns
Maximum clock
pulse frequency
SH
CP
or ST
CP
f
max
Figure 1, 2
MHz
NOTES:
1. Unless otherwise stated, all typical values are at T
amb
= 25
°
C.
2. Typical value measured at V
CC
= 3.3V.
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