參數資料
型號: 74LV273
廠商: NXP Semiconductors N.V.
英文描述: Octal D-type flip-flop with reset; positive-edge trigger
中文描述: 八路D型觸發(fā)器的復位觸發(fā)器,積極邊緣觸發(fā)
文件頁數: 7/12頁
文件大小: 117K
代理商: 74LV273
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
1998 May 29
7
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5V * V
CC
at V
CC
V
and V
OH
are the typical output voltage drop that occur with the
output load.
2.7V
3.6V
2.7V and
4.5V
V
M
V
M
1/f
MAX
t
w
t
PHL
t
PLH
CP INPUT
Qn OUTPUT
SV00370
GND
V
OH
V
OL
V
I
Figure 1. The clock (CP) to output (Q
n
) propagation delays, the
clock pulse width and the maximum clock pulse frequency
V
M
MR INPUT
Qn OUTPUT
t
w
t
PHL
t
rem
CP INPUT
SV00372
V
I
GND
V
I
GND
V
OH
V
OL
V
M
V
M
V
M
Figure 2. The master reset (MR) pulse width, the master reset
to output (Q
n
) propagations delay and the master reset to clock
(CP) removal time
Q
n
OUTPUT
tsu
tsu
ìì
ìì
ìì
ìììììì
ìììììì
ìììììì
ìììì
ìììì
ìììì
CP INPUT
D
n
INPUT
V
M
h
V
M
V
M
h
V
I
GND
V
I
GND
V
OH
V
OL
SV00371
Figure 3. Data set-up and hold times for the data input (D
n
)
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
4.5 V
V
CC
50pF
SV00902
Figure 4. Load circuitry for switching times
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