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參數(shù)資料
| 型號(hào)： | 74LV273 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Octal D-type flip-flop with reset; positive-edge trigger |
| 中文描述： | 八路D型觸發(fā)器的復(fù)位觸發(fā)器，積極邊緣觸發(fā) |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 117K |
| 代理商： | 74LV273 |
Philips Semiconductors
Product specification
74LV273
Octal D-type flip-flop with reset; positive edge-trigger
2
1998 May 29
853–1965 19466
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Ideal buffer for MOS microprocessor or memory
Common clock and master reset
Output capability: standard
I
CC
category: MSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV273 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT273.
The 74LV273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
=t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n;
MR to Q
n
C
L
= 15pF
V
CC
= 3.3V
12
13
ns
f
max
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
Maximum clock frequency
110
MHz
Input capacitance
3.5
pF
Power dissipation capacitance per flip-flop
Notes 1 and 2
20
pF
V
CC2
f
o
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
20-Pin Plastic DIL
–40
°
C to +125
°
C
74LV273 N
74LV273 N
SOT146-1
20-Pin Plastic SO
–40
°
C to +125
°
C
74LV273 D
74LV273 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV273 DB
74LV273 DB
SOT339-1
20-Pin Plastic TSSOP
–40
°
C to +125
°
C
74LV273 PW
74LV273PW DH
SOT360-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV273PWDH | Octal D-type flip-flop with reset; positive-edge trigger |
| 74LV27DB | Triple 3-input NOR gate |
| 74LV27 | Triple 3-input NOR gate |
| 74LV27PW | Triple 3-input NOR gate |
| 74LV27PWDH | Triple 3-input NOR gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV273AFPEL-E | 制造商:Renesas 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin SOP T/R |
| 74LV273ATELL-E | 制造商:Renesas 功能描述:Flip Flop D-Type Bus Interface Pos-Edge 1-Element 20-Pin TSSOP T/R |
| 74LV273D | 功能描述:觸發(fā)器 3.3V D-TYPE W/RESET POS RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV273D,112 | 功能描述:觸發(fā)器 3.3V D-TYPE W/RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV273D,118 | 功能描述:觸發(fā)器 3.3V D-TYPE W/RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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