參數(shù)資料
型號(hào): 74LV174PWDH
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 通用總線(xiàn)功能
英文描述: Hex D-type flip-flop with reset; positive-edge trigger
中文描述: LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16
封裝: PLASTIC, SOT403-1, TSSOP-16
文件頁(yè)數(shù): 6/14頁(yè)
文件大小: 121K
代理商: 74LV174PWDH
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
1998 May 20
6
DC CHARACTERISTICS FOR THE LV FAMILY (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
-40
°
C to +85
°
C
-40
°
C to +125
°
C
I
I
Input leakage
current
Quiescent supply
current; MSI
Additional
quiescent supply
current per input
V
CC
= 5.5V; V
I
= V
CC
or GND
1.0
1.0
μ
A
I
CC
V
CC
= 5.5V; V
I
= V
CC
or GND; I
O
= 0
20.0
160
μ
A
I
CC
V
CC
= 2.7V to 3.6V; V
I
= V
CC
–0.6V
500
850
μ
A
NOTE:
1. All typical values are measured at T
amb
= 25
°
C.
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
= 2.5ns; C
L
= 50pF; R
L
= 1K
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°
C
TYP
1
100
34
25
19
2
13
3
80
27
20
15
2
11
3
10
8
6
2
4
3
9
6
5
4
2
–20
–7
–5
–4
2
–3
3
10
4
3
2
2
1
3
LIMITS
–40 to +125
°
C
MIN
41
30
24
16
41
30
24
16
5
5
5
5
26
19
15
10
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
1.2
2.0
2.7
3.0 to 3.6
4.5 to 5.5
MIN
34
25
20
13
34
25
20
13
5
5
5
5
22
16
13
9
MAX
43
31
25
21
43
31
25
21
MAX
53
39
31
26
53
39
31
26
Propagation delay
CP to Q
n
t
PHL/
t
PLH
Figure 1
ns
Propagation delay
MR to Q
n
t
PHL
Figure 2
ns
t
W
Clock pulse width
HIGH to LOW
Figure 1
ns
t
W
Master reset pulse
width LOW
Figure 2
ns
Removal time
MR to CP
t
rem
Figure 2
ns
Set up time
Set-up time
D
n
to CP
t
su
Figure 3
ns
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