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參數(shù)資料
| 型號： | 74LV174PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Hex D-type flip-flop with reset; positive-edge trigger |
| 中文描述： | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SOT403-1, TSSOP-16 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 121K |
| 代理商： | 74LV174PWDH |
Philips Semiconductors
Product specification
74LV174
Hex D-type flip-flop with reset; positive edge-trigger
2
1998 May 20
853–1964 19422
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC
= 2.7V and V
CC
= 3.6V
Typical V
OLP
(output ground bounce)
T
amb
= 25
°
C
Typical V
OHV
(output V
OH
undershoot)
T
amb
= 25
°
C
Output capability: standard
I
CC
category: MSI
0.8V @ V
CC
= 3.3V,
2V @ V
CC
= 3.3V,
DESCRIPTION
The 74LV174 is a low–voltage Si–gate CMOS device and is pin and
function compatible with the 74HC/HCT174.
The 74LV174 has six edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
set–up time prior to the LOW–to–HIGH clock transition, is
transferred to the corresponding output of the flip–flop.
A LOW level on the MR input forces all outputs LOW, independently
of clock or data inputs.
The device is useful for applications requiring true outputs only and
clock and master reset inputs that are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
CP to Q
n
MR to Q
n
C
L
= 15pF
V
CC
= 3.3V
16
13
ns
f
max
C
I
Maximum clock frequency
77
MHz
Input capacitance
3.5
pF
C
PD
Power dissipation capacitance per flip-flop
V
CC
= 3.3V
Notes 1 and 2
17
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
= C
V
CC2
x f
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
= supply voltage in V;
(C
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
V
CC2
f
) where:
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
16-Pin Plastic DIL
–40
°
C to +125
°
C
74LV174 N
74LV174 N
SOT38-4
16-Pin Plastic SO
–40
°
C to +125
°
C
74LV174 D
74LV174 D
SOT109-1
16-Pin Plastic SSOP Type II
–40
°
C to +125
°
C
74LV174 DB
74LV174 DB
SOT338-1
16-Pin Plastic TSSOP
–40
°
C to +125
°
C
74LV174 PW
74LV174PW DH
SOT403-1
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| 74LV20PW | Dual 4-input NAND gate |
| 74LV20PWDH | Sensors |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV174PW-T | 功能描述:觸發(fā)器 HEX D-TYPE MASTER RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74LV175 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR |
| 74LV175D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
| 74LV175DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad D-Type Flip-Flop |
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