- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360485 > 74LV165PWDH (NXP SEMICONDUCTORS) 8-bit parallel-in/serial-out shift register PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LV165PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-bit parallel-in/serial-out shift register |
| 中文描述： | LV/LV-A/LVX/H SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PDSO16 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 137K |
| 代理商： | 74LV165PWDH |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)
Philips Semiconductors
Product specification
74LV165
8-bit parallel-in/serial-out shift register
1998 May 07
8
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V.
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
SV00592
D
7
INPUT
V
M
V
M
V
M
Q
7
OUTPUT
Q
7
OUTPUT
V
OL
V
OL
GND
V
OH
V
OH
V
I
t
PLH
t
PHL
t
PHL
t
PLH
Figure 3. Data input (D
n
) to output (Q
7
or Q
7
) propagation
delays when PL is LOW.
SV00595
V
M
V
M
CP, CE
INPUT
GND
D
S
INPUT
CP, CE
INPUT
GND
GND
V
I
V
I
V
I
stable
V
M
t
h
t
su
(H)
t
W
t
su
(L)
t
su
t
h
t
h
see note
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
Figure 4. Set-up and hold times from the serial data input (D
S
) to
the clock (CP) and the clock enable (CE) inputs, from the clock
enable input (CE) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE).
Note to Figure 4
CE may change only from HIGH-to-LOW while CP is LOW. The
shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00593
V
M
V
M
D
n
INPUT
PL INPUT
GND
GND
V
I
V
I
t
su
t
su
t
H
t
H
Figure 5. Set-up and hold times from the data inputs (D
n
)
to the parallel load input (PL).
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
≥
4.5 V
V
CC
50pF
SV00902
Figure 6. Load circuitry for switching times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV165 | 8-bit parallel-in/serial-out shift register(8位并入串出移位寄存器) |
| 74LV174 | Hex D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的六D觸發(fā)器) |
| 74LV174PWDH | Hex D-type flip-flop with reset; positive-edge trigger |
| 74LV175 | Quad D-type flip-flop with reset;positive-edge trigger(上升沿觸發(fā),帶復(fù)位的四D觸發(fā)器) |
| 74LV20PW | Dual 4-input NAND gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV165PW-Q100J | 制造商:NXP Semiconductors 功能描述:74LV165PW-Q100/TSSOP16/REEL13/ - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC SHIFT REGISTER 8BIT 16TSSOP |
| 74LV165PW-T | 功能描述:計(jì)數(shù)器移位寄存器 PRLLEL-LOAD 8BIT S/R RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| 74LV174 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hex D-type flip-flop with reset; positive-edge trigger |
| 74LV174A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:HEX D-TYPE FLIP-FLOPS WITH CLEAR |
| 74LV174D | 功能描述:觸發(fā)器 HEX D-TYPE MASTER RESET RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。