- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄360485 > 74LV161PWDH (NXP SEMICONDUCTORS) Presettable synchronous 4-bit binary counter; asynchronous reset PDF資料下載
參數(shù)資料
| 型號(hào)： | 74LV161PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 中文描述： | LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-403, TSSOP1-16 |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 148K |
| 代理商： | 74LV161PWDH |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
Philips Semiconductors
Presettable synchronous 4-bit binary counter;
asynchronous reset
Product specification
74LV161
1997 May 15
9
AC ELECTRICAL CHARACTERISTICS
(Continued)
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
–35
–12
–9
–7
2
40
58
70
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
h
Hold time
PE CEP CET to
D
n
, PE, CEP, CET to
CP
Figures 4 – 6
0
0
0
14
19
24
0
0
0
12
16
20
ns
Maximum clock
pulse frequency
f
max
Figures 1, 6
MHz
NOTES:
1. Unless otherwise stated, all typical values are measured at T
amb
= 25
°
C
2. Typical values are measured at V
CC
= 3.3 V.
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V;
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the output load.
Q
n
, TC
OUTPUT
t
W
SV00576
V
M
CP INPUT
V
M
t
PLH
t
PHL
1/f
max
V
OL
V
OH
GND
V
I
Figure 1. Clock (CP) to outputs (Q
n
, TC) propagation delays,
the clock pulse width and the maximum clock frequency.
t
rem
SV00577
V
M
MR INPUT
CP INPUT
V
I
V
I
GND
GND
V
OL
V
OH
Q
n
, TC
OUTPUT
V
M
V
M
t
PHL
t
W
Figure 2. Master reset (MR) pulse width,
the master reset to output (Q
n
, TC) propagation delays
and the master reset to clock (CP) removal times.
SV00578
V
M
CET INPUT
TC OUTPUT
V
M
t
PHL
t
PLH
GND
V
I
V
OL
V
OH
Figure 3. Input (CET) to output (TC) propagation delays.
SV00579
V
M
V
M
PE INPUT
CP INPUT
D
n
INPUT
V
M
t
h
t
su
t
su
t
su
t
su
t
h
t
h
t
h
GND
GND
GND
V
I
V
I
V
I
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 4. Set-up and hold times for input (D
n
)
and parallel enable input (PE).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV163 | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163D | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163N | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163PW | Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163PWDH | Presettable synchronous 4-bit binary counter; synchronous reset |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV161PW-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Synchronous Up Counter |
| 74LV163 | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; synchronous reset |
| 74LV163A | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:4BIT SYNCHRONOUS BINARY |
| 74LV163ARGYR | 制造商: 功能描述: 制造商:undefined 功能描述: |
| 74LV163D | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Presettable synchronous 4-bit binary counter; synchronous reset |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。