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| 型號： | 74LV161PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Presettable synchronous 4-bit binary counter; asynchronous reset |
| 中文描述： | LV/LV-A/LVX/H SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16 |
| 封裝： | PLASTIC, SOT-403, TSSOP1-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 148K |
| 代理商： | 74LV161PWDH |
Philips Semiconductors
Presettable synchronous 4-bit binary counter;
asynchronous reset
Product specification
74LV161
1997 May 15
8
AC CHARACTERISTICS
GND = 0V; t
r
= t
f
≤
2.5ns; C
L
= 50pF; R
L
=
1
K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
95
32
24
18
2
115
39
29
22
2
95
32
24
18
2
105
36
26
20
2
55
19
14
10
2
10
8
6
2
14
10
8
2
25
9
6
5
2
25
9
6
5
2
30
10
8
6
2
30
10
8
6
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
PHL/
t
PLH
Propagation delay
CP to Q
n
Figures 1 6
Figures 1, 6
61
45
36
75
55
44
ns
y
t
PHL/
t
PLH
Propagation delay
CP to TC
Figures 1 6
Figures 1, 6
75
55
44
90
66
53
ns
y
t
PHL/
t
PLH
Propagation delay
MR to Q
n
Figures 2 6
Figures 2, 6
61
45
36
75
55
44
ns
t
PHL/
t
PLH
Propagation delay
MR to TC
Figures 2 6
Figures 2, 6
68
50
40
82
60
48
ns
y
t
PHL/
t
PLH
Propagation delay
CET to TC
Figures 1 6
Figures 1, 6
36
26
21
44
33
26
ns
y
Clock pulse width
HIGH or LOW
34
25
20
34
25
20
41
30
24
41
30
24
t
w
Figures 2, 6
ns
Master reset width;
LOW
t
w
Figures 2, 6
ns
t
rem
Removal time
MR to CP
Figures 2 6
Figures 2, 6
22
16
13
26
19
15
ns
t
su
Set-up time
D
n
to CP
Figures 4 6
Figures 4, 6
22
16
13
26
19
15
ns
t
su
Set-up time
PE to CP
Figures 4 6
Figures 4, 6
22
16
13
26
19
15
ns
t
su
Set-up time
CEP, CET to CP
Figures 5 6
Figures 5, 6
22
16
13
26
19
15
ns
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