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參數(shù)資料
| 型號： | 74LV109DB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK flip-flop with set and reset; positive-edge trigger |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 124K |
| 代理商： | 74LV109DB |
Philips Semiconductors
Product specification
74LV109
Dual JK flip-flop with set and reset; positive-edge trigger
1998 Apr 20
5
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
-40
°
C to +85
°
C
TYP
1
-40
°
C to +125
°
C
MIN
0.9
UNIT
MIN
0.9
MAX
MAX
HIGH level I
voltage
t
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 to 3.6 V
V
CC
= 1.2 V
V
CC
= 2.0 V
V
CC
= 2.7 to 3.6 V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
–I
O
= 100
μ
A
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
–I
O
= 100
μ
A
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
–I
O
= 100
μ
A
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
–I
O
= 100
μ
A
V
IH
1.4
1.4
V
2.0
2.0
LOW level I
voltage
t
0.3
0.3
V
IL
0.6
0.6
V
0.8
0.8
1.2
V
OH
HIGH level output
voltage; all outputs
1.8
2.0
1.8
V
2.5
2.7
2.5
2.8
3.0
2.8
V
OH
HIGH level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
–I
O
= 6mA
2.40
2.82
2.20
V
V
CC
= 1.2 V; V
I
= V
IH
or V
IL;
I
O
= 100
μ
A
V
CC
= 2.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
μ
A
V
CC
= 2.7 V; V
I
= V
IH
or V
IL;
I
O
= 100
μ
A
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 100
μ
A
0
V
OL
LOW level output
voltage; all outputs
0
0.2
0.2
V
0
0.2
0.2
0
0.2
0.2
V
OL
LOW level output
voltage;
STANDARD
outputs
V
CC
= 3.0 V; V
I
= V
IH
or V
IL;
I
O
= 6mA
0.25
0.40
0.50
V
I
I
Input leakage
current
Quiescent supply
current; flip-flops
Additional
quiescent supply
current per input
V
CC
= 3.6 V; V
I
= V
CC
or GND
1.0
1.0
μ
A
I
CC
V
CC
= 3.6V; V
I
= V
CC
or GND; I
O
= 0
20.0
80
μ
A
I
CC
V
CC
= 2.7 V to 3.6 V; V
I
= V
CC
– 0.6 V
500
850
μ
A
NOTE:
1. All typical values are measured at T
amb
= 25
°
C.
AC CHARACTERISTICS
GND
=
0V; t
r
=
t
f
≤
2.5ns; C
L
=
50pF; R
L
=
1K
CONDITION
LIMITS
SYMBOL
PARAMETER
WAVEFORM
–40 to +85
°
C
TYP
1
90
31
23
18
2
55
19
14
10
2
–40 to +125
°
C
MIN
UNIT
V
CC
(V)
1.2
2.0
2.7
3.0 to 3.6
1.2
2.0
2.7
3.0 to 3.6
MIN
MAX
MAX
t
PHL
/t
PLH
Propagation delay
nCP to nQ, nQ
Figure 1
58
43
34
70
51
41
ns
y
t
PLH
Propagation delay
nS
D
to nQ
Figure 2
36
26
21
44
33
26
ns
y
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相關代理商/技術參數(shù) |
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|---|---|
| 74LV109DB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:J-K-Type Flip-Flop |
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| 74LV109N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109PW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109PWDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual JK flip-flop with set and reset; positive-edge trigger |
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