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參數(shù)資料
| 型號(hào)： | 74LV107DB |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | CMOS |
| 中文描述： | LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 |
| 封裝： | 5.30 MM, PLASTIC, MO-150AB, SOT-337-1, SSOP2-14 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 121K |
| 代理商： | 74LV107DB |
Philips Semiconductors
Product specification
74LV107
Dual JK flip-flop with reset; negative-edge trigger
1998 Apr 20
7
AC WAVEFORMS
V
M
= 1.5 V at V
CC
≥
2.7 V and
≤
3.6 V;
V
M
= 0.5
×
V
CC
at V
CC
<
2.7 V and
≥
4.5 V;
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
SV00504
1/fmax
th
th
tPLH
tPHL
tPLH
tPHL
tW
tsu
tsu
VM
VM
VM
VM
nJ, nK
INPUT
GND
nCP
INPUT
GND
nQ
OUTPUT
VI
VI
VOH
VOH
nQ
OUTPUT
VOL
VOL
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the J and K to nCP set-up and hold times
and the maximum clock pulse frequency.
SV00502
tW
tPHL
tPLH
trem
VM
VM
VM
nR
INPUT
GND
nCP
INPUT
GND
nQ
OUTPUT
VOH
nQ
VI
VI
VOH
VOL
VOL
OUTPUT
Figure 2. Reset (nR) input to output (nQ, nQ) propagation
delays, the reset pulse width and the nR to nCP removal time.
TEST CIRCUIT
PULSE
GENERATOR
R
T
V
l
D.U.T.
V
O
C
L
R
L
= 1k
V
cc
Test Circuit for Outputs
DEFINITIONS
R
L
= Load resistor
C
L
= Load capacitance includes jig and probe capacitiance
R
T
= Termination resistance should be equal to Z
OUT
of pulse generators.
V
CC
V
I
< 2.7V
2.7–3.6V
V
CC
2.7V
TEST
t
PLH/
t
PHL
≥
4.5 V
V
CC
50pF
SV00902
Figure 3. Load circuitry for switching times.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74LV107N | Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107PW | CLP SINE |
| 74LV107PWDH | CLP SINE |
| 74LV109 | Dual JK flip-flop with set and reset; positive-edge trigger |
| 74LV109D | CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74LV107DB-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV107D-T | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:J-K-Type Flip-Flop |
| 74LV107N | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107PW | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
| 74LV107PWDH | 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Dual JK flip-flop with reset; negative-edge trigger |
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