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參數(shù)資料
| 型號： | 74HCT74 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual D-TYPE flip-flop with set and reset;positive-edge trigger(帶指令集和復(fù)位的雙D觸發(fā)器；上升沿觸發(fā)) |
| 中文描述： | 雙D型觸發(fā)器設(shè)置和復(fù)位觸發(fā)器，積極邊緣觸發(fā)器（帶指令集和復(fù)位的雙?觸發(fā)器;上升沿觸發(fā)） |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 98K |
| 代理商： | 74HCT74 |
1998 Feb 23
2
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
FEATURES
Output capability: standard
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (S
D
) and reset (R
D
) inputs; also complementary Q and
Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
14
15
16
76
3.5
24
15
18
18
59
3.5
29
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
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