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參數(shù)資料
| 型號(hào)： | 74HCT7403 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 4-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 4位× 64字的FIFO寄存器，三態(tài) |
| 文件頁(yè)數(shù)： | 4/28頁(yè) |
| 文件大?。?/td> | 163K |
| 代理商： | 74HCT7403 |
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September 1993
4
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Fig.4 Functional diagram.
MGA679
DIR
OE
SI
MR
DnA
4
DIR
SI
DOR
SO
DATA INPUT
A
A
4
SOA
DORA
QnA
7403
FIFO A
DIR
OE
SI
MR
DnB
B
B
4
SOB
QnB
DORB
7403
FIFO B
DATA OUTPUT
OE
MR
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D
0
to D
3
is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q
0
to Q
3
).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
Expanded format
(see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
Serial expansion
Serial expansion is accomplished by:
tying the data outputs of the first
device to the data inputs of the
second device
connecting the DOR pin of the first
device to the SI pin of the second
device
connecting the SO pin of the first
device to the DIR pin of the second
device.
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| 7403 | 4-Bit x 64-word FIFO register; 3-state |
| 7403 | BASIC SIGNAL PROCESSOR |
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| 74HC7404 | 5-Bit x 64-word FIFO register; 3-state |
| 74HC7404D | 5-Bit x 64-word FIFO register; 3-state |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT7403D | 功能描述:寄存器 4-BIT X64 WORD FIFO REG 3-ST RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D,512 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D,518 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類(lèi)型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D-Q100,51 | 制造商:NXP Semiconductors 功能描述:FIFO Register Single 4-CH CMOS 16-Pin SO T/R 制造商:NXP Semiconductors 功能描述:74HCT7403D-Q100/SO16/REEL13DP/ - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FIFO REGISTER 4X64 3ST 16SOIC |
| 74HCT7403D-Q100,518 | 制造商:NXP Semiconductors 功能描述: |
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