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參數(shù)資料
| 型號(hào)： | 74HCT7403 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Dual 4-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 4位× 64字的FIFO寄存器，三態(tài) |
| 文件頁(yè)數(shù)： | 28/28頁(yè) |
| 文件大小： | 163K |
| 代理商： | 74HCT7403 |
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September 1993
28
Philips Semiconductors
Product specification
4-Bit x 64-word FIFO register; 3-state
74HC/HCT7403
Sequence 2 (FIFO
B
runs full)
After the MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIR
B
remains LOW due to FIFO
B
being full (5). DOR
A
goes LOW due to FIFO
A
being empty.
Sequence 3 (FIFO
A
runs full)
When 65 words are shifted in, DOR
A
remains HIGH due to valid data remaining at the output of FIFO
A
. Q
nA
remains
HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
Sequence 4 (both FIFOs full, starting SHIFT-OUT process)
SI
A
is held HIGH and two SO
B
pulses are applied (8). These pulses shift out two words and thus allow two empty
locations to bubble-up to the input stage of FIFO
B
, and proceed to FIFO
A
(9). When the first empty location arrives at the
input of FIFO
A
, a DIR
A
pulse is generated (10) and a new word is shifted into FIFO
A
. SI
A
is made LOW and now the
second empty location reaches the input stage of FIFO
A
, after which DIR
A
remains HIGH (11).
Sequence 5 (FIFO
A
runs empty)
At the start of sequence 5 FIFO
A
contains 63 valid words due to two words being shifted out and one word being shifted
in, in sequence 4. An additional series of SO
B
pulses are applied. After 63 SO
B
pulses, all words from FIFO
A
are shifted
into FIFO
B
. DOR
A
remains LOW (12).
Sequence 6 (FIFO
B
runs empty)
After the next SO
B
pulse, DIR
B
remains HIGH due to the input stage of FIFO
B
being empty. After another 63 SO
B
pulses,
DOR
B
remains LOW due to both FIFOs being empty (14). Additional SO
B
pulses have no effect. The last word remains
available at the output Q
n
.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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| 7403 | 4-Bit x 64-word FIFO register; 3-state |
| 7403 | BASIC SIGNAL PROCESSOR |
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| 74HC7404 | 5-Bit x 64-word FIFO register; 3-state |
| 74HC7404D | 5-Bit x 64-word FIFO register; 3-state |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT7403D | 功能描述:寄存器 4-BIT X64 WORD FIFO REG 3-ST RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D,512 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D,518 | 功能描述:寄存器 4-BIT X64 WORD FIFO RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| 74HCT7403D-Q100,51 | 制造商:NXP Semiconductors 功能描述:FIFO Register Single 4-CH CMOS 16-Pin SO T/R 制造商:NXP Semiconductors 功能描述:74HCT7403D-Q100/SO16/REEL13DP/ - Tape and Reel 制造商:NXP Semiconductors 功能描述:IC FIFO REGISTER 4X64 3ST 16SOIC |
| 74HCT7403D-Q100,518 | 制造商:NXP Semiconductors 功能描述: |
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