參數(shù)資料
型號(hào): 74HCT40105PW
廠商: NXP SEMICONDUCTORS
元件分類: FIFO
英文描述: 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
中文描述: 16 X 4 OTHER FIFO, 120 ns, PDSO16
封裝: 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16
文件頁數(shù): 12/25頁
文件大?。?/td> 200K
代理商: 74HCT40105PW
1998 Jan 23
12
Philips Semiconductors
Product specification
4-bit x 16-word FIFO register
74HC/HCT40105
Master reset applied with FIFO full
Fig.8
Waveforms showing the MR input to DIR, DOR output
propagation delays and the MR pulse width.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Notes to
Fig.8
1.
DIR LOW, output ready HIGH;
assume FIFO is full.
MR pulse HIGH; clears FIFO.
DIR goes HIGH; flag indicates
input prepared for valid data.
DOR drops LOW; flag indicates
FIFO empty.
2.
3.
4.
Shifting out sequence; FIFO full to FIFO empty
Fig.9
Waveforms showing the SO input to DIR output propagation
delay. The SO pulse width and SO maximum pulse frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
.
HCT : V
M
= 1.3 V; V
I
= GND to 3 V.
Notes to
Fig.9
1.
DOR HIGH; no data transfer in
progress, valid data is present at
output stage.
SO set HIGH.
SO is set LOW; data in the input
stage is unloaded, and new data
replaces it as empty location
“bubbles-up” to input stage.
DOR drops LOW; output stage
“busy”.
DOR goes HIGH; transfer
process completed, valid data
present at output after the
specified propagation delay.
Repeat process to unloaded the
3rd through to the 16th word from
FIFO.
DOR remains LOW; FIFO is
empty.
2.
3.
4.
5.
6.
7.
相關(guān)PDF資料
PDF描述
74HC40105 4-bit x 16-word FIFO register
74HCT4015 8-Bit Parallel-Load Shift Registers 16-SO -40 to 85
74HC4015 Dual 4-bit serial-in/parallel-out shift register
74HCT4016 Quad bilateral switches(四雙向開關(guān))
74HC4016 Quad bilateral switches
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