參數(shù)資料
型號: 74HCT297
廠商: NXP Semiconductors N.V.
英文描述: Digital phase-locked-loop filter
中文描述: 數(shù)字鎖相環(huán)回路濾波器
文件頁數(shù): 3/12頁
文件大?。?/td> 101K
代理商: 74HCT297
September 1993
3
Philips Semiconductors
Product specification
Digital phase-locked-loop filter
74HC/HCT297
The carry and borrow pulses go to the
increment/decrement (I/D) circuit which, in the absence of
any carry or borrow pulses has an output that is 1/2 of the
input clock (I/D
CP
). The input clock is just a multiple, 2N, of
the loop centre frequency. In response to a carry or borrow
pulse, the I/D circuit will either add or delete a pulse at
I/D
OUT
. Thus the output of the I/D circuit will be
Nf
c
+
(k
d
e
Mf
c
)/2K.
The output of the N-counter (or the output of the
phase-locked-loop) is thus: f
o
= f
c
+
(k
d
φ
e
Mf
c
)/2KN.
If this result is compared to the equation for a first-order
analog phase-locked-loop, the digital equivalent of the
gain of the VCO is just Mf
c
/2KN or f
c
/K for M = 2N.
Thus the simple first-order phase-locked-loop with an
adjustable K-counter is the equivalent of an analog
phase-locked-loop with a programmable VCO gain.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL/
t
PLH
propagation delay
I/D
CP
to I/D
OUT
φ
A
1
,
φ
B to XORPD
OUT
φ
B,
φ
A
2
to ECPD
OUT
maximum clock frequency
K
CP
I/D
CP
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V
15
13
19
18
13
19
ns
ns
ns
f
max
63
41
3.5
18
68
40
3.5
19
MHz
MHz
pF
pF
C
I
C
PD
notes 1 and 2
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