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參數(shù)資料
| 型號： | 74HCT112 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-Line To 3-Line Priority Encoders 16-SO -40 to 85 |
| 中文描述： | 雙JK觸發(fā)器設(shè)置和復(fù)位觸發(fā)器，負邊沿觸發(fā) |
| 文件頁數(shù)： | 2/15頁 |
| 文件大小： | 106K |
| 代理商： | 74HCT112 |
1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
FEATURES
Asynchronous set and reset
Output capability: standard
I
CC
category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nS
D
) and reset (nR
D
) inputs.
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
nS
D
to nQ, nQ
nR
D
to nQ, nQ
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop
C
L
= 15 pF; V
CC
= 5 V
17
15
18
66
3.5
27
19
15
19
70
3.5
30
ns
ns
ns
MHz
pF
pF
f
max
C
I
C
PD
notes 1 and 2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC11 | Triple 3-input AND gate |
| 74HCT11 | 8-Line To 3-Line Priority Encoders 16-SO -40 to 85 |
| 74HC123 | Dual retriggerable monostable multivibrator with reset |
| 74HCT123 | 8-Line To 1-Line Data Selectors/Multiplexers 16-SOIC -40 to 85 |
| 74HC132 | Quad 2-input NAND Schmitt trigger |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HCT112D | 功能描述:觸發(fā)器 DUAL JK F/F NEG-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT112D,652 | 功能描述:觸發(fā)器 DUAL JK F/F NEG-EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT112D,653 | 功能描述:觸發(fā)器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| 74HCT112D652 | 制造商:NXP Semiconductors 功能描述:IC JK FLIP FLOP DUAL 19NS SOIC-14 |
| 74HCT112DB | 功能描述:觸發(fā)器 DUAL J-K NEG EDGE RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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