參數(shù)資料
型號: 74HC74DG
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS
中文描述: HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: LEAD FREE, SOIC-14
文件頁數(shù): 7/8頁
文件大小: 143K
代理商: 74HC74DG
74HC74
http://onsemi.com
7
PACKAGE DIMENSIONS
TSSOP
14
CASE 948G
01
ISSUE B
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MIN
4.90
4.30
0.05
0.50
0.65 BSC
0.50
0.09
0.09
0.19
0.19
6.40 BSC
0
MAX
5.10
4.50
1.20
0.15
0.75
MIN
0.193
0.169
0.002
0.020
0.026 BSC
0.020
0.004
0.004
0.007
0.007
0.252 BSC
0
MAX
0.200
0.177
0.047
0.006
0.030
INCHES
MILLIMETERS
0.60
0.20
0.16
0.30
0.25
0.024
0.008
0.006
0.012
0.010
8
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE
W
.
S
U
0.15 (0.006) T
2X
L/2
S
U
M
0.10 (0.004)
V
S
T
L
U
SEATING
PLANE
0.10 (0.004)
T
SECTION N
N
DETAIL E
J J1
K
ééé
DETAIL E
F
M
W
0.25 (0.010)
8
14
7
1
PIN 1
IDENT.
H
G
A
D
C
B
S
U
0.15 (0.006) T
V
14X REF
N
N
7.06
0.36
14X
1.26
0.65
PITCH
DIMENSIONS: MILLIMETERS
1
SOLDERING FOOTPRINT*
*For additional information on our Pb
Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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74HC74 Dual D Flip-Flop with Set and Reset(帶設(shè)置和復(fù)位的雙D觸發(fā)器)
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