參數(shù)資料
型號(hào)： 74HC7404D
廠商： NXP SEMICONDUCTORS
元件分類： FIFO
英文描述： 5-Bit x 64-word FIFO register; 3-state
中文描述： 64 X 5 OTHER FIFO, 98 ns, PDSO20
封裝： PLASTIC, SO-20
文件頁(yè)數(shù)： 16/28頁(yè)
文件大?。?/td> 131K
代理商： 74HC7404D
September 1993
16
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
With FIFO empty; SO is held HIGH in anticipation
Notes to
Fig.11
1.
2.
3.
4.
FIFO is initially empty, SO is held HIGH
SI pulse; loads data into FIFO and initiates ripple through process
DOR flag signals the arrival of valid data at the output stage
Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Q
n
output
DOR goes LOW; data shift-out is complete, FIFO is empty again
SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
5.
6.
Fig.11 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Q
n
output.
handbook, full pagewidth
SI INPUT
MGA669
3
5
Qn OUTPUT
DOR OUTPUT
VM
(1)
2
ripple through
delay
VM
(1)
6
4
SO INPUT
tPLH
tPLH
tPHL
VM
(1)
1
tW
(1) HC
:
V
M
= 50%; V
I
= GND to V
.
V
M
= 1.3 V; V
I
= GND to 3 V.
HCT :
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