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參數(shù)資料
| 型號： | 74HC7404D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | FIFO |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 64 X 5 OTHER FIFO, 98 ns, PDSO20 |
| 封裝： | PLASTIC, SO-20 |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 131K |
| 代理商： | 74HC7404D |
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September 1993
12
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
Notes to
Fig.7
1.
2.
3.
4.
5.
6.
DIR initially HIGH; FIFO is prepared for valid data
SI set HIGH; data loaded into input stage
DIR goes LOW, input stage “busy”
SI set LOW; data from first location “ripple through”
DIR goes HIGH, status flag indicates FIFO prepared for additional data
Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
Fig.7
Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
handbook, full pagewidth
MGA659
VM
(1)
1/
f max
W
t
tPHL
tPLH
VM
(1)
1st word
2nd word
64th word
7
3
1
5
6
4
2
SI INPUT
Dn INPUT
DIR OUTPUT
(1) HC
:
V
M
= 50%; V
I
= GND to V
.
V
M
= 1.3 V; V
I
= GND to 3 V.
HCT :
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