- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360463 > 74HC7404 (NXP Semiconductors N.V.) 5-Bit x 64-word FIFO register; 3-state PDF資料下載
參數(shù)資料
| 型號(hào)： | 74HC7404 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 5-Bit x 64-word FIFO register; 3-state |
| 中文描述： | 5位× 64字FIFO寄存器，三態(tài) |
| 文件頁(yè)數(shù)： | 28/28頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | 74HC7404 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)當(dāng)前第28頁(yè)
September 1993
28
Philips Semiconductors
Product specification
5-Bit x 64-word FIFO register; 3-state
74HC/HCT7404
Sequence 2 (FIFO
B
runs full)
After the MR pulse, a series of 64 SI
pulses are applied. When 64 words
are shifted in, DIR
B
remains LOW due
to FIFO
B
being full (5). DOR
A
goes
LOW due to FIFO
A
being empty.
Sequence 3 (FIFO
A
runs full)
When 65 words are shifted in, DOR
A
remains HIGH due to valid data
remaining at the output of FIFO
A
. Q
nA
remains HIGH, being the polarity of
the 65th data word (6). After the 128th
SI pulse, DIR remains LOW and both
FIFOs are full (7). Additional pulses
have no effect.
Sequence 4 (both FIFOs full,
starting SHIFT-OUT process)
SI
A
is held HIGH and two SO
B
pulses
are applied (8). These pulses shift out
two words and thus allow two empty
locations to bubble-up to the input
stage of FIFO
B
, and proceed to FIFO
A
(9). When the first empty location
arrives at the input of FIFO
A
, a DIR
A
pulse is generated (10) and a new
word is shifted into FIFO
A
. SI
A
is
made LOW and now the second
empty location reaches the input
stage of FIFO
A
, after which DIR
A
remains HIGH (11).
Sequence 5 (FIFO
A
runs empty)
At the start of sequence 5 FIFO
A
contains 63 valid words due to two
words being shifted out and one word
being shifted in, in sequence 4. An
additional series of SO
B
pulses are
applied. After 63 SO
B
pulses, all
words from FIFO
A
are shifted into
FIFO
B
. DOR
A
remains LOW (12).
Sequence 6 (FIFO
B
runs empty)
After the next SO
B
pulse, DIR
B
remains HIGH due to the input stage
of FIFO
B
being empty. After another
63 SO
B
pulses, DOR
B
remains LOW
due to both FIFOs being empty (14).
Additional SO
B
pulses have no effect.
The last word remains available at the
output Q
n
.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic
Package Outlines”
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 74HC7404D | 5-Bit x 64-word FIFO register; 3-state |
| 74HC7404N | 5-Bit x 64-word FIFO register; 3-state |
| 74HCT7404 | Dual 4-Input Positive-NAND Gates 14-TSSOP -40 to 85 |
| 74HCT7404D | 5-Bit x 64-word FIFO register; 3-state |
| 74HCT7404N | 5-Bit x 64-word FIFO register; 3-state |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 74HC747 | 制造商:NXP Semiconductors 功能描述: |
| 74HC74A | 功能描述:DIE CM FLIP-FLOP DUAL D 制造商:fairchild/micross components 系列:74HC 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:25 |
| 74HC74ADTR2 | 制造商:ON Semiconductor 功能描述: |
| 74HC74AM | 制造商:Texas Instruments 功能描述: |
| 74HC74AP | 制造商:. 功能描述: 制造商:Toshiba America Electronic Components 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。